| Message ID | 20230810132904.367418-1-robert.marko@sartura.hr |
|---|---|
| State | Accepted |
| Commit | b5ed7a5c1fdb3981713f7b637b72aa390c3db036 |
| Headers | show |
| Series | ARM: dts: qcom: ipq4019: correct SDHCI XO clock | expand |
On Thu, 10 Aug 2023 15:28:21 +0200, Robert Marko wrote: > Using GCC_DCD_XO_CLK as the XO clock for SDHCI controller is not correct, > it seems that I somehow made a mistake of passing it instead of the fixed > XO clock. > > Applied, thanks! [1/1] ARM: dts: qcom: ipq4019: correct SDHCI XO clock commit: 43a0ce827528bdc7f4d38d48d13987db24a4e7b1 Best regards,
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 5492aeed14a5..450179fbed32 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -231,8 +231,7 @@ sdhci: mmc@7824900 { interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <8>; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_DCD_XO_CLK>; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&xo>; clock-names = "iface", "core", "xo"; status = "disabled"; };
Using GCC_DCD_XO_CLK as the XO clock for SDHCI controller is not correct, it seems that I somehow made a mistake of passing it instead of the fixed XO clock. Fixes: 04b3b72b5b8f ("ARM: dts: qcom: ipq4019: Add SDHCI controller node") Signed-off-by: Robert Marko <robert.marko@sartura.hr> --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)