| Message ID | 20230811110150.229966-1-robert.marko@sartura.hr |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] ARM: dts: qcom: ipq4019: correct SDHCI XO clock | expand |
On Fri, 11 Aug 2023 13:01:16 +0200, Robert Marko wrote: > Using GCC_DCD_XO_CLK as the XO clock for SDHCI controller is not correct, > it seems that I somehow made a mistake of passing it instead of the fixed > XO clock. > > Applied, thanks! [1/1] ARM: dts: qcom: ipq4019: correct SDHCI XO clock commit: b5ed7a5c1fdb3981713f7b637b72aa390c3db036 Best regards,
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 5492aeed14a5..80c04915f0e8 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -231,9 +231,12 @@ sdhci: mmc@7824900 { interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <8>; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_DCD_XO_CLK>; - clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names = "iface", + "core", + "xo"; status = "disabled"; };
Using GCC_DCD_XO_CLK as the XO clock for SDHCI controller is not correct, it seems that I somehow made a mistake of passing it instead of the fixed XO clock. Fixes: 04b3b72b5b8f ("ARM: dts: qcom: ipq4019: Add SDHCI controller node") Signed-off-by: Robert Marko <robert.marko@sartura.hr> --- Changes in v2: * Make clocks and clock-names one-per-line --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)