| Message ID | 20230811214031.171020-9-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Implement cortex-a710 | expand |
On Fri, 11 Aug 2023 at 22:41, Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/tcg/cpu64.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > index b0cac05be6..0054bb6dfa 100644 > --- a/target/arm/tcg/cpu64.c > +++ b/target/arm/tcg/cpu64.c > @@ -573,6 +573,18 @@ static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { > .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > }; > > +/* > + * TODO: For a write with bit 1 set, do something with arm_reset_cpu(). > + * In the meantime, "the bit is strictly a request", so we are in spec > + * just ignoring writes. > + */ > +static const ARMCPRegInfo rmr_reginfo = { > + .name = "RMR_EL3", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 2, > + .access = PL3_RW, .type = ARM_CP_CONST, > + .resetvalue = 1, /* [31:2] RES0, [1] reset 0, [0] RES1 */ > +}; > + This register is architectural (but optional), not implementation-specific. There's also an RMR_EL1 and RMR_EL2 depending on which ELs are implemented. If we want to implement this we should do it in helper.c alongside RVBAR_EL1 (which has a similar "only the register for the highest EL exists" setup). But I'd be tempted to continue to ignore this, unless there's some firmware out there that really wants to see the register. PS: you don't want arm_reset_cpu(), since we know that we are running on the exact CPU we want to reset. cpu_reset() will do. (And I don't think we can implement "reset into AArch32" currently.) thanks -- PMM
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index b0cac05be6..0054bb6dfa 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -573,6 +573,18 @@ static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, }; +/* + * TODO: For a write with bit 1 set, do something with arm_reset_cpu(). + * In the meantime, "the bit is strictly a request", so we are in spec + * just ignoring writes. + */ +static const ARMCPRegInfo rmr_reginfo = { + .name = "RMR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 2, + .access = PL3_RW, .type = ARM_CP_CONST, + .resetvalue = 1, /* [31:2] RES0, [1] reset 0, [0] RES1 */ +}; + static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) { /* @@ -581,6 +593,7 @@ static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) */ define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo); + define_one_arm_cp_reg(cpu, &rmr_reginfo); } static void aarch64_neoverse_n1_initfn(Object *obj)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/cpu64.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)