| Message ID | 20230726104249.534210-1-quic_ipkumar@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] PCI: qcom: Set max payload size 256 bytes for IPQ9574 | expand |
On Wed, Jul 26, 2023 at 04:12:49PM +0530, Praveenkumar I wrote: > This patch sets 256 bytes as payload size for IPQ9574. This allows > PCIe RC to use the max payload size when a capable link partner is > connected. I'm confused because this patch doesn't apply to v6.7-rc1, and I don't see qcom_pcie_post_init_1_27_0() or IPQ9574 mentioned in the git history. Maybe this depends on some out-of-tree patch? I think this commit log should explain why the existing code in the PCI core doesn't do what's needed. Is there something qcom-specific about this issue? Maybe an example including the DEVCAP Max_Payload_Size Supported and the DEVCTL Max_Payload_Size for both ends of the link would help understand what's going wrong. Does this setting get lost after suspend? Does it need to be updated again after suspend/resume? > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > [v2]: > Dropped cover letter for this patch. Configured the max payload > in the post_init of IPQ9574 instead for early fixup. > > drivers/pci/controller/dwc/pcie-qcom.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 8ee7c2b5de27..739c0d514a96 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1145,6 +1145,15 @@ static int qcom_pcie_post_init(struct qcom_pcie *pcie) > > static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) > { > + struct dw_pcie *pci = pcie->pci; > + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + u32 val; > + > + val = readl(pci->dbi_base + offset + PCI_EXP_DEVCTL); > + val &= ~PCI_EXP_DEVCTL_PAYLOAD; > + val |= PCI_EXP_DEVCTL_PAYLOAD_256B; > + writel(val, pci->dbi_base + offset + PCI_EXP_DEVCTL); > + > writel(SLV_ADDR_SPACE_SZ_1_27_0, > pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); > > -- > 2.34.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8ee7c2b5de27..739c0d514a96 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1145,6 +1145,15 @@ static int qcom_pcie_post_init(struct qcom_pcie *pcie) static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) { + struct dw_pcie *pci = pcie->pci; + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; + + val = readl(pci->dbi_base + offset + PCI_EXP_DEVCTL); + val &= ~PCI_EXP_DEVCTL_PAYLOAD; + val |= PCI_EXP_DEVCTL_PAYLOAD_256B; + writel(val, pci->dbi_base + offset + PCI_EXP_DEVCTL); + writel(SLV_ADDR_SPACE_SZ_1_27_0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
This patch sets 256 bytes as payload size for IPQ9574. This allows PCIe RC to use the max payload size when a capable link partner is connected. Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> --- [v2]: Dropped cover letter for this patch. Configured the max payload in the post_init of IPQ9574 instead for early fixup. drivers/pci/controller/dwc/pcie-qcom.c | 9 +++++++++ 1 file changed, 9 insertions(+)