diff mbox series

[v2,2/6] dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt names

Message ID 20230724091927.123847-3-biju.das.jz@bp.renesas.com
State Accepted
Commit b7a8f1f7a8a25e09aaefebb6251a77f44cda638b
Headers show
Series Add RZ/G2UL MTU3a support | expand

Commit Message

Biju Das July 24, 2023, 9:19 a.m. UTC
As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow
interrupt names starts with 'tci' instead of 'tgi'.

Fix this documentation issue by replacing below overflow/underflow
interrupt names:
 - tgiv0->tciv0
 - tgiv1->tciv1
 - tgiu1->tciu1
 - tgiv2->tciv2
 - tgiu2->tciu2
 - tgiv3->tciv3
 - tgiv4->tciv4
 - tgiv6->tciv6
 - tgiv7->tciv7
 - tgiv8->tciv8
 - tgiu8->tciu8

Fixes: 0a9d6b54297e ("dt-bindings: timer: Document RZ/G2L MTU3a bindings")
Cc: stable@kernel.org
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
v1->v2:
 * Added Ack from Conor Dooley.
---
 .../bindings/timer/renesas,rz-mtu3.yaml       | 38 +++++++++----------
 1 file changed, 19 insertions(+), 19 deletions(-)

Comments

Geert Uytterhoeven July 25, 2023, 8:52 a.m. UTC | #1
Hi Biju,

On Mon, Jul 24, 2023 at 11:19 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow
> interrupt names starts with 'tci' instead of 'tgi'.
>
> Fix this documentation issue by replacing below overflow/underflow
> interrupt names:
>  - tgiv0->tciv0
>  - tgiv1->tciv1
>  - tgiu1->tciu1
>  - tgiv2->tciv2
>  - tgiu2->tciu2
>  - tgiv3->tciv3
>  - tgiv4->tciv4
>  - tgiv6->tciv6
>  - tgiv7->tciv7
>  - tgiv8->tciv8
>  - tgiu8->tciu8
>
> Fixes: 0a9d6b54297e ("dt-bindings: timer: Document RZ/G2L MTU3a bindings")
> Cc: stable@kernel.org
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v1->v2:
>  * Added Ack from Conor Dooley.

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
> +++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml

> @@ -197,18 +197,18 @@ properties:
>        - const: tgib6
>        - const: tgic6
>        - const: tgid6
> -      - const: tgiv6
> +      - const: tciv6
>        - const: tgia7
>        - const: tgib7
>        - const: tgic7
>        - const: tgid7
> -      - const: tgiv7
> +      - const: tciv7
>        - const: tgia8
>        - const: tgib8
>        - const: tgic8
>        - const: tgid8
> -      - const: tgiv8
> -      - const: tgiu8
> +      - const: tciv8
> +      - const: tciu8

According to the documentation, there is no underflow interrupt for
channel 8?

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Biju Das July 25, 2023, 9:11 a.m. UTC | #2
Hi Geert Uytterhoeven,

Thanks for the feedback.

> Subject: Re: [PATCH v2 2/6] dt-bindings: timer: renesas,rz-mtu3: Fix
> overflow/underflow interrupt names
> 
> Hi Biju,
> 
> On Mon, Jul 24, 2023 at 11:19 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow
> > interrupt names starts with 'tci' instead of 'tgi'.
> >
> > Fix this documentation issue by replacing below overflow/underflow
> > interrupt names:
> >  - tgiv0->tciv0
> >  - tgiv1->tciv1
> >  - tgiu1->tciu1
> >  - tgiv2->tciv2
> >  - tgiu2->tciu2
> >  - tgiv3->tciv3
> >  - tgiv4->tciv4
> >  - tgiv6->tciv6
> >  - tgiv7->tciv7
> >  - tgiv8->tciv8
> >  - tgiu8->tciu8
> >
> > Fixes: 0a9d6b54297e ("dt-bindings: timer: Document RZ/G2L MTU3a
> > bindings")
> > Cc: stable@kernel.org
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > v1->v2:
> >  * Added Ack from Conor Dooley.
> 
> Thanks for your patch!
> 
> > --- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
> > +++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
> 
> > @@ -197,18 +197,18 @@ properties:
> >        - const: tgib6
> >        - const: tgic6
> >        - const: tgid6
> > -      - const: tgiv6
> > +      - const: tciv6
> >        - const: tgia7
> >        - const: tgib7
> >        - const: tgic7
> >        - const: tgid7
> > -      - const: tgiv7
> > +      - const: tciv7
> >        - const: tgia8
> >        - const: tgib8
> >        - const: tgic8
> >        - const: tgid8
> > -      - const: tgiv8
> > -      - const: tgiu8
> > +      - const: tciv8
> > +      - const: tciu8
> 
> According to the documentation, there is no underflow interrupt for
> channel 8?

I got confirmation from HW manual team.

Table 8.2 in the HW manual is correct. ie, underflow interrupt is present
for channel 8.

They are going to correct Table16.78 in Chapter 16 MTU3a.

Cheers,
Biju
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
index eb2d5ebe4df0..670a2ebaacdb 100644
--- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
@@ -169,27 +169,27 @@  properties:
       - const: tgib0
       - const: tgic0
       - const: tgid0
-      - const: tgiv0
+      - const: tciv0
       - const: tgie0
       - const: tgif0
       - const: tgia1
       - const: tgib1
-      - const: tgiv1
-      - const: tgiu1
+      - const: tciv1
+      - const: tciu1
       - const: tgia2
       - const: tgib2
-      - const: tgiv2
-      - const: tgiu2
+      - const: tciv2
+      - const: tciu2
       - const: tgia3
       - const: tgib3
       - const: tgic3
       - const: tgid3
-      - const: tgiv3
+      - const: tciv3
       - const: tgia4
       - const: tgib4
       - const: tgic4
       - const: tgid4
-      - const: tgiv4
+      - const: tciv4
       - const: tgiu5
       - const: tgiv5
       - const: tgiw5
@@ -197,18 +197,18 @@  properties:
       - const: tgib6
       - const: tgic6
       - const: tgid6
-      - const: tgiv6
+      - const: tciv6
       - const: tgia7
       - const: tgib7
       - const: tgic7
       - const: tgid7
-      - const: tgiv7
+      - const: tciv7
       - const: tgia8
       - const: tgib8
       - const: tgic8
       - const: tgid8
-      - const: tgiv8
-      - const: tgiu8
+      - const: tciv8
+      - const: tciu8
 
   clocks:
     maxItems: 1
@@ -285,16 +285,16 @@  examples:
                    <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
                    <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
                    <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
-      interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
+      interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0",
                         "tgif0",
-                        "tgia1", "tgib1", "tgiv1", "tgiu1",
-                        "tgia2", "tgib2", "tgiv2", "tgiu2",
-                        "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
-                        "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
+                        "tgia1", "tgib1", "tciv1", "tciu1",
+                        "tgia2", "tgib2", "tciv2", "tciu2",
+                        "tgia3", "tgib3", "tgic3", "tgid3", "tciv3",
+                        "tgia4", "tgib4", "tgic4", "tgid4", "tciv4",
                         "tgiu5", "tgiv5", "tgiw5",
-                        "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
-                        "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
-                        "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
+                        "tgia6", "tgib6", "tgic6", "tgid6", "tciv6",
+                        "tgia7", "tgib7", "tgic7", "tgid7", "tciv7",
+                        "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8";
       clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
       power-domains = <&cpg>;
       resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;