| Message ID | 20230724091927.123847-5-biju.das.jz@bp.renesas.com |
|---|---|
| State | Accepted |
| Commit | 4c188fa183ebb45238ef16504c4c7606955cf9d4 |
| Headers | show |
| Series | Add RZ/G2UL MTU3a support | expand |
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH v2 4/6] arm64: dts: renesas: r9a07g044: Update > overfow/underflow IRQ names for MTU3 channels > > Hi Biju, > > On Mon, Jul 24, 2023 at 11:19 AM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow > > interrupt names starts with 'tci' instead of 'tgi'. > > > > Replace the below overflow/underflow interrupt names: > > - tgiv0->tciv0 > > - tgiv1->tciv1 > > - tgiu1->tciu1 > > - tgiv2->tciv2 > > - tgiu2->tciu2 > > - tgiv3->tciv3 > > - tgiv4->tciv4 > > - tgiv6->tciv6 > > - tgiv7->tciv7 > > - tgiv8->tciv8 > > - tgiu8->tciu8 > > > > Fixes: 26336d66d021 ("arm64: dts: renesas: r9a07g044: Add MTU3a node") > > Fixes: dd123dd01def ("arm64: dts: renesas: r9a07g054: Add MTU3a node") > > These were added in v6.5-rc1, so it would be good to get this fixed > before the final release of v6.5 (i.e. before I sent my first PR for > v6.6 later this week). > > > Cc: stable@kernel.org > > No need to CC stable. OK. > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > v1->v2: > > * No change. > > Thanks for your patch! > > --- > > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 16 ++++++++-------- > > arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 16 ++++++++-------- > > 2 files changed, 16 insertions(+), 16 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > index 232910e07444..66f68fc2b241 100644 > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > @@ -223,20 +223,20 @@ mtu3: timer@10001200 { > > <GIC_SPI 212 > IRQ_TYPE_EDGE_RISING>, > > <GIC_SPI 213 > IRQ_TYPE_EDGE_RISING>; > > interrupt-names = "tgia0", "tgib0", "tgic0", > "tgid0", > > - "tgiv0", "tgie0", "tgif0", > > - "tgia1", "tgib1", "tgiv1", > "tgiu1", > > - "tgia2", "tgib2", "tgiv2", > "tgiu2", > > + "tciv0", "tgie0", "tgif0", > > + "tgia1", "tgib1", "tciv1", > "tciu1", > > + "tgia2", "tgib2", "tciv2", > > + "tciu2", > > "tgia3", "tgib3", "tgic3", > "tgid3", > > - "tgiv3", > > + "tciv3", > > "tgia4", "tgib4", "tgic4", > "tgid4", > > - "tgiv4", > > + "tciv4", > > "tgiu5", "tgiv5", "tgiw5", > > "tgia6", "tgib6", "tgic6", > "tgid6", > > - "tgiv6", > > + "tciv6", > > "tgia7", "tgib7", "tgic7", > "tgid7", > > - "tgiv7", > > + "tciv7", > > "tgia8", "tgib8", "tgic8", > "tgid8", > > - "tgiv8", "tgiu8"; > > + "tciv8", "tciu8"; > > clocks = <&cpg CPG_MOD > R9A07G044_MTU_X_MCK_MTU3>; > > power-domains = <&cpg>; > > resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; > > While SPI 213 is documented to be used for TCIU8, the actual MTU3a > documentation does not mention this interrupt. Current change is fine. HW manual team is going to correct Table16.78 in Chapter 16 MTU3a. Cheers, Biju
On Tue, Jul 25, 2023 at 11:14 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > On Mon, Jul 24, 2023 at 11:19 AM Biju Das <biju.das.jz@bp.renesas.com> > > wrote: > > > As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow > > > interrupt names starts with 'tci' instead of 'tgi'. > > > > > > Replace the below overflow/underflow interrupt names: > > > - tgiv0->tciv0 > > > - tgiv1->tciv1 > > > - tgiu1->tciu1 > > > - tgiv2->tciv2 > > > - tgiu2->tciu2 > > > - tgiv3->tciv3 > > > - tgiv4->tciv4 > > > - tgiv6->tciv6 > > > - tgiv7->tciv7 > > > - tgiv8->tciv8 > > > - tgiu8->tciu8 > > > > > > Fixes: 26336d66d021 ("arm64: dts: renesas: r9a07g044: Add MTU3a node") > > > Fixes: dd123dd01def ("arm64: dts: renesas: r9a07g054: Add MTU3a node") > > While SPI 213 is documented to be used for TCIU8, the actual MTU3a > > documentation does not mention this interrupt. > > Current change is fine. > HW manual team is going to correct Table16.78 in Chapter 16 MTU3a. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue as a fix for v6.5. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 232910e07444..66f68fc2b241 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -223,20 +223,20 @@ mtu3: timer@10001200 { <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", - "tgiv0", "tgie0", "tgif0", - "tgia1", "tgib1", "tgiv1", "tgiu1", - "tgia2", "tgib2", "tgiv2", "tgiu2", + "tciv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tciv1", "tciu1", + "tgia2", "tgib2", "tciv2", "tciu2", "tgia3", "tgib3", "tgic3", "tgid3", - "tgiv3", + "tciv3", "tgia4", "tgib4", "tgic4", "tgid4", - "tgiv4", + "tciv4", "tgiu5", "tgiv5", "tgiw5", "tgia6", "tgib6", "tgic6", "tgid6", - "tgiv6", + "tciv6", "tgia7", "tgib7", "tgic7", "tgid7", - "tgiv7", + "tciv7", "tgia8", "tgib8", "tgic8", "tgid8", - "tgiv8", "tgiu8"; + "tciv8", "tciu8"; clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 2eba3a8a100d..1f1d481dc783 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -223,20 +223,20 @@ mtu3: timer@10001200 { <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", - "tgiv0", "tgie0", "tgif0", - "tgia1", "tgib1", "tgiv1", "tgiu1", - "tgia2", "tgib2", "tgiv2", "tgiu2", + "tciv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tciv1", "tciu1", + "tgia2", "tgib2", "tciv2", "tciu2", "tgia3", "tgib3", "tgic3", "tgid3", - "tgiv3", + "tciv3", "tgia4", "tgib4", "tgic4", "tgid4", - "tgiv4", + "tciv4", "tgiu5", "tgiv5", "tgiw5", "tgia6", "tgib6", "tgic6", "tgid6", - "tgiv6", + "tciv6", "tgia7", "tgib7", "tgic7", "tgid7", - "tgiv7", + "tciv7", "tgia8", "tgib8", "tgic8", "tgid8", - "tgiv8", "tgiu8"; + "tciv8", "tciu8"; clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow interrupt names starts with 'tci' instead of 'tgi'. Replace the below overflow/underflow interrupt names: - tgiv0->tciv0 - tgiv1->tciv1 - tgiu1->tciu1 - tgiv2->tciv2 - tgiu2->tciu2 - tgiv3->tciv3 - tgiv4->tciv4 - tgiv6->tciv6 - tgiv7->tciv7 - tgiv8->tciv8 - tgiu8->tciu8 Fixes: 26336d66d021 ("arm64: dts: renesas: r9a07g044: Add MTU3a node") Fixes: dd123dd01def ("arm64: dts: renesas: r9a07g054: Add MTU3a node") Cc: stable@kernel.org Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 16 ++++++++-------- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-)