| Message ID | 20230718064246.12429-1-quic_ninanaik@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets | expand |
On Tue, Jul 18, 2023 at 08:32:59AM -0700, Bjorn Andersson wrote: > On Tue, Jul 18, 2023 at 12:12:46PM +0530, Ninad Naik wrote: > > SA8775 and newer target have added support for an increased number of > > interrupt targets. To implement this change, the intr_target field, which > > is used to configure the interrupt target in the interrupt configuration > > register is increased from 3 bits to 4 bits. > > > > In accordance to these updates, a new intr_target_width member is > > introduced in msm_pingroup structure. This member stores the value of > > width of intr_target field in the interrupt configuration register. This > > value is used to dynamically calculate and generate mask for setting the > > intr_target field. By default, this mask is set to 3 bit wide, to ensure > > backward compatibility with the older targets. > > > > Changes in v2 : > > ----------------- > > - Changed initial definition of intr_target_mask variable to use GENMASK(). > > - Update commit subject appropiately. > > - Add Fixes tag. > > - v1 : https://lore.kernel.org/all/20230714061010.15817-1-quic_ninanaik@quicinc.com/ > > Thanks for adding a good changelog, very much appreciated. The changelog > should be added below the '---' line though, as it typically don't add > value to the git history (except drivers/gpu/* which wants it here...). > > Perhaps Linus can drop it as he applies the patch, no need to resubmit > unless he ask you to. > > Thanks, > Bjorn > Gentle ping on this one... but then I realized that linusw isn't CC'ed on this patch directly, and I'm unsure of what the workflow is for pinctrl. ./scripts/get_maintainer.pl shows he should have been in the CC list ideally :) Maybe send a v3 with the changelog dropped from the actual message (i.e. follow Bjorn's advice), and make sure to include the folks get_maintainer tells you to so this gets picked up (or maybe just saying Linus' name will make him appear out of the woodworks if we're lucky): ahalaney@fedora ~/git/linux-next (git)-[7de73ad15b73] % b4 am 20230718064246.12429-1-quic_ninanaik@quicinc.com Grabbing thread from lore.kernel.org/all/20230718064246.12429-1-quic_ninanaik@quicinc.com/t.mbox.gz Analyzing 3 messages in the thread Checking attestation on all messages, may take a moment... --- ✓ [PATCH v2] pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets --- ✓ Signed: DKIM/quicinc.com --- Total patches: 1 --- Link: https://lore.kernel.org/r/20230718064246.12429-1-quic_ninanaik@quicinc.com Base: applies clean to current tree git checkout -b v2_20230718_quic_ninanaik_quicinc_com HEAD git am ./v2_20230718_quic_ninanaik_pinctrl_qcom_add_intr_target_width_field_to_support_increased_number_of_in.mbx ahalaney@fedora ~/git/linux-next (git)-[7de73ad15b73] % ./scripts/get_maintainer.pl ./v2_20230718_quic_ninanaik_pinctrl_qcom_add_intr_target_width_field_to_support_increased_number_of_in.mbx Andy Gross <agross@kernel.org> (maintainer:ARM/QUALCOMM SUPPORT) Bjorn Andersson <andersson@kernel.org> (maintainer:ARM/QUALCOMM SUPPORT) Konrad Dybcio <konrad.dybcio@linaro.org> (maintainer:ARM/QUALCOMM SUPPORT,blamed_fixes:1/1=100%) Linus Walleij <linus.walleij@linaro.org> (maintainer:PIN CONTROL SUBSYSTEM,blamed_fixes:1/1=100%) Bartosz Golaszewski <bartosz.golaszewski@linaro.org> (blamed_fixes:1/1=100%) Yadu MG <quic_ymg@quicinc.com> (blamed_fixes:1/1=100%) Prasad Sodagudi <quic_psodagud@quicinc.com> (blamed_fixes:1/1=100%) linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT) linux-gpio@vger.kernel.org (open list:PIN CONTROL SUBSYSTEM) linux-kernel@vger.kernel.org (open list) ahalaney@fedora ~/git/linux-next (git)-[7de73ad15b73] % I'm eager to get this fix in so I can describe a missing IRQ or two wrt ethernet GPIOs and submit that without stating the dependency on this fix! :) Thanks, Andrew
On 8/9/2023 2:36 AM, Andrew Halaney wrote: > On Tue, Jul 18, 2023 at 08:32:59AM -0700, Bjorn Andersson wrote: >> On Tue, Jul 18, 2023 at 12:12:46PM +0530, Ninad Naik wrote: >>> SA8775 and newer target have added support for an increased number of >>> interrupt targets. To implement this change, the intr_target field, which >>> is used to configure the interrupt target in the interrupt configuration >>> register is increased from 3 bits to 4 bits. >>> >>> In accordance to these updates, a new intr_target_width member is >>> introduced in msm_pingroup structure. This member stores the value of >>> width of intr_target field in the interrupt configuration register. This >>> value is used to dynamically calculate and generate mask for setting the >>> intr_target field. By default, this mask is set to 3 bit wide, to ensure >>> backward compatibility with the older targets. >>> >>> Changes in v2 : >>> ----------------- >>> - Changed initial definition of intr_target_mask variable to use GENMASK(). >>> - Update commit subject appropiately. >>> - Add Fixes tag. >>> - v1 : https://lore.kernel.org/all/20230714061010.15817-1-quic_ninanaik@quicinc.com/ >> >> Thanks for adding a good changelog, very much appreciated. The changelog >> should be added below the '---' line though, as it typically don't add >> value to the git history (except drivers/gpu/* which wants it here...). >> >> Perhaps Linus can drop it as he applies the patch, no need to resubmit >> unless he ask you to. >> >> Thanks, >> Bjorn >> > > Gentle ping on this one... but then I realized that linusw isn't CC'ed > on this patch directly, and I'm unsure of what the workflow is for > pinctrl. ./scripts/get_maintainer.pl shows he should have been in the CC > list ideally :) > > Maybe send a v3 with the changelog dropped from the actual message (i.e. > follow Bjorn's advice), and make sure to include the folks > get_maintainer tells you to so this gets picked up (or maybe just saying > Linus' name will make him appear out of the woodworks if we're lucky): My bad on this one, I'll immediately send a v3 along with addressing the changelog suggestion mentioned by Bjorn. > > ahalaney@fedora ~/git/linux-next (git)-[7de73ad15b73] % b4 am 20230718064246.12429-1-quic_ninanaik@quicinc.com > Grabbing thread from lore.kernel.org/all/20230718064246.12429-1-quic_ninanaik@quicinc.com/t.mbox.gz > Analyzing 3 messages in the thread > Checking attestation on all messages, may take a moment... > --- > ✓ [PATCH v2] pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets > --- > ✓ Signed: DKIM/quicinc.com > --- > Total patches: 1 > --- > Link: https://lore.kernel.org/r/20230718064246.12429-1-quic_ninanaik@quicinc.com > Base: applies clean to current tree > git checkout -b v2_20230718_quic_ninanaik_quicinc_com HEAD > git am ./v2_20230718_quic_ninanaik_pinctrl_qcom_add_intr_target_width_field_to_support_increased_number_of_in.mbx > ahalaney@fedora ~/git/linux-next (git)-[7de73ad15b73] % ./scripts/get_maintainer.pl ./v2_20230718_quic_ninanaik_pinctrl_qcom_add_intr_target_width_field_to_support_increased_number_of_in.mbx > Andy Gross <agross@kernel.org> (maintainer:ARM/QUALCOMM SUPPORT) > Bjorn Andersson <andersson@kernel.org> (maintainer:ARM/QUALCOMM SUPPORT) > Konrad Dybcio <konrad.dybcio@linaro.org> (maintainer:ARM/QUALCOMM SUPPORT,blamed_fixes:1/1=100%) > Linus Walleij <linus.walleij@linaro.org> (maintainer:PIN CONTROL SUBSYSTEM,blamed_fixes:1/1=100%) > Bartosz Golaszewski <bartosz.golaszewski@linaro.org> (blamed_fixes:1/1=100%) > Yadu MG <quic_ymg@quicinc.com> (blamed_fixes:1/1=100%) > Prasad Sodagudi <quic_psodagud@quicinc.com> (blamed_fixes:1/1=100%) > linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT) > linux-gpio@vger.kernel.org (open list:PIN CONTROL SUBSYSTEM) > linux-kernel@vger.kernel.org (open list) > ahalaney@fedora ~/git/linux-next (git)-[7de73ad15b73] % > > I'm eager to get this fix in so I can describe a missing IRQ or two > wrt ethernet GPIOs and submit that without stating the dependency > on this fix! :) > > Thanks, > Andrew > Thanks, Ninad
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 2585ef2b2793..115b83e2d8e6 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1038,6 +1038,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct msm_pinctrl *pctrl = gpiochip_get_data(gc); const struct msm_pingroup *g; + u32 intr_target_mask = GENMASK(2, 0); unsigned long flags; bool was_enabled; u32 val; @@ -1074,13 +1075,15 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) * With intr_target_use_scm interrupts are routed to * application cpu using scm calls. */ + if (g->intr_target_width) + intr_target_mask = GENMASK(g->intr_target_width - 1, 0); + if (pctrl->intr_target_use_scm) { u32 addr = pctrl->phys_base[0] + g->intr_target_reg; int ret; qcom_scm_io_readl(addr, &val); - - val &= ~(7 << g->intr_target_bit); + val &= ~(intr_target_mask << g->intr_target_bit); val |= g->intr_target_kpss_val << g->intr_target_bit; ret = qcom_scm_io_writel(addr, val); @@ -1090,7 +1093,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) d->hwirq); } else { val = msm_readl_intr_target(pctrl, g); - val &= ~(7 << g->intr_target_bit); + val &= ~(intr_target_mask << g->intr_target_bit); val |= g->intr_target_kpss_val << g->intr_target_bit; msm_writel_intr_target(val, pctrl, g); } diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 5e4410bed823..1d2f2e904da1 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -59,6 +59,7 @@ struct pinctrl_pin_desc; * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt * status. * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. + * @intr_target_width: Number of bits used for specifying interrupt routing target. * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from * this gpio should get routed to the KPSS processor. * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. @@ -100,6 +101,7 @@ struct msm_pingroup { unsigned intr_ack_high:1; unsigned intr_target_bit:5; + unsigned intr_target_width:5; unsigned intr_target_kpss_val:5; unsigned intr_raw_status_bit:5; unsigned intr_polarity_bit:5; diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index 8a5cd15512b9..8fdea25d8d67 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -46,6 +46,7 @@ .intr_enable_bit = 0, \ .intr_status_bit = 0, \ .intr_target_bit = 5, \ + .intr_target_width = 4, \ .intr_target_kpss_val = 3, \ .intr_raw_status_bit = 4, \ .intr_polarity_bit = 1, \
SA8775 and newer target have added support for an increased number of interrupt targets. To implement this change, the intr_target field, which is used to configure the interrupt target in the interrupt configuration register is increased from 3 bits to 4 bits. In accordance to these updates, a new intr_target_width member is introduced in msm_pingroup structure. This member stores the value of width of intr_target field in the interrupt configuration register. This value is used to dynamically calculate and generate mask for setting the intr_target field. By default, this mask is set to 3 bit wide, to ensure backward compatibility with the older targets. Changes in v2 : ----------------- - Changed initial definition of intr_target_mask variable to use GENMASK(). - Update commit subject appropiately. - Add Fixes tag. - v1 : https://lore.kernel.org/all/20230714061010.15817-1-quic_ninanaik@quicinc.com/ Fixes: 4b6b18559927 ("pinctrl: qcom: add the tlmm driver sa8775p platforms") Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride Signed-off-by: Ninad Naik <quic_ninanaik@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> --- drivers/pinctrl/qcom/pinctrl-msm.c | 9 ++++++--- drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++ drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1 + 3 files changed, 9 insertions(+), 3 deletions(-)