| Message ID | 20230712151153.81965-1-biju.das.jz@bp.renesas.com |
|---|---|
| State | Accepted |
| Commit | fe7297bf011bf6910d76010ba1763daf1286cbf4 |
| Headers | show |
| Series | arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0 | expand |
On Wed, Jul 12, 2023 at 5:12 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > The PHY interrupt (INT_N) pin is connected to IRQ0 for ETH0. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.6. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index e56f5ce6b0d9..56ff92453976 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> / { @@ -81,6 +82,8 @@ phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -139,7 +142,8 @@ eth0_pins: eth0 { <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ - <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(0, 0, 1)>; /* IRQ0 */ }; gpio-sd0-pwr-en-hog {
The PHY interrupt (INT_N) pin is connected to IRQ0 for ETH0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)