diff mbox series

arm64: dts: renesas: r9a07g0{4,5}4: Add support for enabling MTU3

Message ID 20230703132929.356009-1-biju.das.jz@bp.renesas.com
State New
Headers show
Series arm64: dts: renesas: r9a07g0{4,5}4: Add support for enabling MTU3 | expand

Commit Message

Biju Das July 3, 2023, 1:29 p.m. UTC 
Add support for MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC EVK.

The MTU3a PWM pins are muxed with spi1 pins and counter external input
phase clock pins are muxed with scif2 pins. Disable these IPs when MTU3
macro is enabled.

Apart from this, the counter Z phase clock signal is muxed with the
SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
is enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../boot/dts/renesas/r9a07g044l2-smarc.dts    | 36 +++++++++++++++++++
 .../boot/dts/renesas/r9a07g054l2-smarc.dts    | 36 +++++++++++++++++++
 .../dts/renesas/rzg2l-smarc-pinfunction.dtsi  | 14 ++++++++
 3 files changed, 86 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
index bc2af6c92ccd..03cbae78d640 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
@@ -12,7 +12,43 @@ 
 #include "rz-smarc-common.dtsi"
 #include "rzg2l-smarc.dtsi"
 
+#define MTU3	0
+#define MTU3_COUNTER_Z_PHASE_SIGNAL	0
+#if (!MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as MTU3=0"
+#endif
+
 / {
 	model = "Renesas SMARC EVK based on r9a07g044l2";
 	compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
 };
+
+#if MTU3
+&mtu3 {
+	pinctrl-0 = <&mtu3_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&scif2 {
+	status = "disabled";
+};
+
+#if MTU3_COUNTER_Z_PHASE_SIGNAL
+/* SDHI cd pin is used for counter Z phase signal */
+&mtu3_pins {
+	mtu3-zphase-clk {
+		pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */
+	};
+};
+
+&sdhi1 {
+	status = "disabled";
+};
+#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
+
+&spi1 {
+	status = "disabled";
+};
+#endif /* MTU3 */
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
index 3d01a4cf0fbe..4186bfe739fa 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
@@ -12,7 +12,43 @@ 
 #include "rz-smarc-common.dtsi"
 #include "rzg2l-smarc.dtsi"
 
+#define MTU3	0
+#define MTU3_COUNTER_Z_PHASE_SIGNAL	0
+#if (!MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as MTU3=0"
+#endif
+
 / {
 	model = "Renesas SMARC EVK based on r9a07g054l2";
 	compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054";
 };
+
+#if MTU3
+&mtu3 {
+	pinctrl-0 = <&mtu3_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&scif2 {
+	status = "disabled";
+};
+
+#if MTU3_COUNTER_Z_PHASE_SIGNAL
+/* SDHI cd pin is used for counter Z phase signal */
+&mtu3_pins {
+	mtu3-zphase-clk {
+		pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */
+	};
+};
+
+&sdhi1 {
+	status = "disabled";
+};
+#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
+
+&spi1 {
+	status = "disabled";
+};
+#endif /* MTU3 */
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
index 9085d8c76ce1..e8fbadd44af9 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -53,6 +53,20 @@  i2c3_pins: i2c3 {
 			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
 	};
 
+	mtu3_pins: mtu3 {
+		mtu3-ext-clk-input-pin {
+			pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
+				 <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */
+		};
+
+		mtu3-pwm {
+			pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
+				 <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
+				 <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
+				 <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
+		};
+	};
+
 	scif0_pins: scif0 {
 		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
 			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */