| Message ID | 20230707155849.86649-1-biju.das.jz@bp.renesas.com |
|---|---|
| State | Accepted |
| Commit | 5d7de61ff17f152fb34db1347f53a80d41f511de |
| Headers | show |
| Series | arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3 | expand |
On Fri, Jul 7, 2023 at 5:59 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2LC SMARC > EVK. > > The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when > PMOD_MTU3 macro is enabled. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.6. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index f67a6f125d9c..0b90367b6d1e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -35,6 +35,18 @@ /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ #define PMOD1_SER0 1 +/* + * To enable MTU3a PWM on PMOD0, + * - Set DIP-Switch SW1-4 to Off position. + * - Set SW_RSPI_CAN macro to 0. + * - Set PMOD_MTU3 macro to 1. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && SW_RSPI_CAN) +#error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive" +#endif + #include "r9a07g044c2.dtsi" #include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index a78a8def363e..92c64d58349f 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -50,6 +50,15 @@ i2c2_pins: i2c2 { <RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */ }; + mtu3_pins: mtu3 { + mtu3-pwm { + pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */ + <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */ + <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */ + <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */ + }; + }; + scif0_pins: scif0 { pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 6818fd49b2be..83fce96a2575 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -11,7 +11,6 @@ #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" - / { aliases { serial1 = &scif1; @@ -129,6 +128,19 @@ wm8978: codec@1a { }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&spi1 { + status = "disabled"; +}; +#endif + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2LC SMARC EVK. The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when PMOD_MTU3 macro is enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 12 ++++++++++++ .../boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 9 +++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 14 +++++++++++++- 3 files changed, 34 insertions(+), 1 deletion(-)