@@ -507,7 +507,7 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
savediv / 2 - 1);
}
- if (sai->soc_data->max_register >= FSL_SAI_MCTL) {
+ if (sai->soc_data->mclk_en_gates_clock) {
/* SAI is in master mode at this point, so enable MCLK */
regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
@@ -1513,6 +1513,7 @@ static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
.reg_offset = 0,
.mclk0_is_mclk1 = false,
.flags = 0,
+ .mclk_en_gates_clock = false,
.max_register = FSL_SAI_RMR,
};
@@ -1524,6 +1525,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
.reg_offset = 0,
.mclk0_is_mclk1 = true,
.flags = 0,
+ .mclk_en_gates_clock = false,
.max_register = FSL_SAI_RMR,
};
@@ -1535,6 +1537,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.flags = PMQOS_CPU_LATENCY,
+ .mclk_en_gates_clock = false,
.max_register = FSL_SAI_RMR,
};
@@ -1546,6 +1549,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.flags = 0,
+ .mclk_en_gates_clock = false,
.max_register = FSL_SAI_RMR,
};
@@ -1557,6 +1561,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
.reg_offset = 0,
.mclk0_is_mclk1 = false,
.flags = 0,
+ .mclk_en_gates_clock = false,
.max_register = FSL_SAI_RMR,
};
@@ -1568,6 +1573,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = {
.mclk0_is_mclk1 = false,
.pins = 8,
.flags = 0,
+ .mclk_en_gates_clock = true,
.max_register = FSL_SAI_MCTL,
};
@@ -1579,6 +1585,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = {
.mclk0_is_mclk1 = false,
.pins = 8,
.flags = 0,
+ .mclk_en_gates_clock = false,
.max_register = FSL_SAI_MDIV,
};
@@ -1590,6 +1597,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
.mclk0_is_mclk1 = false,
.pins = 8,
.flags = 0,
+ .mclk_en_gates_clock = false,
.max_register = FSL_SAI_MDIV,
.mclk_with_tere = true,
};
@@ -1602,6 +1610,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
.mclk0_is_mclk1 = false,
.pins = 4,
.flags = PMQOS_CPU_LATENCY,
+ .mclk_en_gates_clock = false,
.max_register = FSL_SAI_RTCAP,
};
@@ -1613,6 +1622,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx93_data = {
.mclk0_is_mclk1 = false,
.pins = 4,
.flags = 0,
+ .mclk_en_gates_clock = false,
.max_register = FSL_SAI_MCTL,
.max_burst = {8, 8},
};
@@ -232,6 +232,7 @@ struct fsl_sai_soc_data {
bool use_edma;
bool mclk0_is_mclk1;
bool mclk_with_tere;
+ bool mclk_en_gates_clock;
unsigned int fifo_depth;
unsigned int pins;
unsigned int reg_offset;