Message ID | 20230630062318.12114-1-duke_xinanwen@163.com |
---|---|
State | Accepted |
Commit | 1cad976a1be9e97ceca5797b7e1000e2f1a9980e |
Headers | show |
Series | [v6] bus: mhi: host: pci_generic: Add support for Quectel RM520N-GL modem | expand |
On Thu, Jun 29, 2023 at 11:23:18PM -0700, Duke Xin(辛安文) wrote: > Add MHI interface definition for RM520 product based on Qualcomm SDX6X chip > > Signed-off-by: Duke Xin(辛安文) <duke_xinanwen@163.com> Applied to mhi-next! - Mani > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> > --- > Changelog > > v5 -> v6 > > * Update commit message to include the changelog and reviewd tag. > > v4 -> v5 > > * Add patch CC to mhi@lists.linux.dev. > > v3 -> v4 > > * Limit character length to 75 characters and adjusted "project" description to "product". > > v2 -> v3 > > * Sorted add rm520 id in mhi_pci_id_table and modify commit message. > > v1 -> v2 > > * Use [modem_quectel_em1xx_config] compatible instead of duplicating the configuration. > --- > drivers/bus/mhi/host/pci_generic.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c > index 70e37c490150..1e7caa62f114 100644 > --- a/drivers/bus/mhi/host/pci_generic.c > +++ b/drivers/bus/mhi/host/pci_generic.c > @@ -352,6 +352,16 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { > .sideband_wake = true, > }; > > +static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { > + .name = "quectel-rm5xx", > + .edl = "qcom/prog_firehose_sdx6x.elf", > + .config = &modem_quectel_em1xx_config, > + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, > + .dma_data_width = 32, > + .mru_default = 32768, > + .sideband_wake = true, > +}; > + > static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { > MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), > MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), > @@ -591,6 +601,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { > .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, > { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ > .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, > + /* RM520N-GL (sdx6x), eSIM */ > + { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), > + .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, > { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ > .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, > /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ > -- > 2.25.1 >
diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index 70e37c490150..1e7caa62f114 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -352,6 +352,16 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { .sideband_wake = true, }; +static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { + .name = "quectel-rm5xx", + .edl = "qcom/prog_firehose_sdx6x.elf", + .config = &modem_quectel_em1xx_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32, + .mru_default = 32768, + .sideband_wake = true, +}; + static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), @@ -591,6 +601,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + /* RM520N-GL (sdx6x), eSIM */ + { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), + .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, /* T99W175 (sdx55), Both for eSIM and Non-eSIM */