@@ -50,8 +50,8 @@ static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv)
ctx = mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE);
/* check if HW active or not */
- cg_status = readl(dev->reg_base[0]);
- if ((cg_status & VDEC_HW_ACTIVE) != 0) {
+ cg_status = readl(dev->reg_base[0] + VDEC_HW_ACTIVE_ADDR);
+ if ((cg_status & VDEC_HW_ACTIVE_MASK) != 0) {
mtk_v4l2_err("DEC ISR, VDEC active is not 0x0 (0x%08x)",
cg_status);
return IRQ_HANDLED;
@@ -75,8 +75,8 @@ static irqreturn_t mtk_vdec_hw_irq_handler(int irq, void *priv)
ctx = mtk_vcodec_get_curr_ctx(dev->main_dev, dev->hw_idx);
/* check if HW active or not */
- cg_status = readl(dev->reg_base[VDEC_HW_SYS]);
- if (cg_status & VDEC_HW_ACTIVE) {
+ cg_status = readl(dev->reg_base[VDEC_HW_SYS] + VDEC_HW_ACTIVE_ADDR);
+ if (cg_status & VDEC_HW_ACTIVE_MASK) {
mtk_v4l2_err("vdec active is not 0x0 (0x%08x)",
cg_status);
return IRQ_HANDLED;
@@ -12,7 +12,8 @@
#include "mtk_vcodec_drv.h"
-#define VDEC_HW_ACTIVE 0x10
+#define VDEC_HW_ACTIVE_ADDR 0x0
+#define VDEC_HW_ACTIVE_MASK BIT(4)
#define VDEC_IRQ_CFG 0x11
#define VDEC_IRQ_CLR 0x10
#define VDEC_IRQ_CFG_REG 0xa4
The VDEC_HW_ACTIVE bit is located at offset 0, bit 4 of the VDECSYS iospace. Only the mask was previously defined, with the address being implicit. Explicitly define the address, and append a '_MASK' suffix to the mask, to make accesses to this bit clearer. This commit brings no functional change. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> --- Changes in v4: - Made use of BIT() macro for mask Changes in v3: - Added this commit drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c | 4 ++-- drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c | 4 ++-- drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h | 3 ++- 3 files changed, 6 insertions(+), 5 deletions(-)