diff mbox series

[RFC,7/7] ARM: dts: stm32: add dfsdm iio suppport

Message ID 20230623140944.2613002-8-olivier.moysan@foss.st.com
State New
Headers show
Series iio: add iio backend device type | expand

Commit Message

Olivier Moysan June 23, 2023, 2:09 p.m. UTC 
This DT is an example of backend iio device use for STM32 DFSDM.
DFSDM filter0 has a single input channel, while filter1 is configured
for scan mode with two input channels.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
---
 arch/arm/boot/dts/stm32mp157c-ev1.dts | 62 +++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index ba8e9d9a42fa..ebd67a219df2 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -73,6 +73,24 @@  panel_backlight: panel-backlight {
 		default-on;
 		status = "okay";
 	};
+
+	sd_adc0: simple-sd-adc0 {
+		compatible = "sd-modulator";
+		io-backend-cells = <0>;
+		vref-supply = <&v3v3>;
+	};
+
+	sd_adc1: simple-sd-adc1 {
+		compatible = "sd-modulator";
+		io-backend-cells = <0>;
+		vref-supply = <&v3v3>;
+	};
+
+	sd_adc2: simple-sd-adc2 {
+		compatible = "sd-modulator";
+		io-backend-cells = <0>;
+		vref-supply = <&v3v3>;
+	};
 };
 
 &cec {
@@ -99,6 +117,50 @@  dcmi_0: endpoint {
 	};
 };
 
+&dfsdm {
+	spi-max-frequency = <2048000>;
+
+	clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
+	clock-names = "dfsdm", "audio";
+	status = "disabled";
+
+	dfsdm0: filter@0 {
+		compatible = "st,stm32-dfsdm-adc";
+		st,filter-order = <3>;
+		status = "okay";
+
+		channel@1 {
+			reg = <1>;
+			label = "in1";
+			st,adc-channel-types = "SPI_R";
+			st,adc-channel-clk-src = "CLKOUT";
+			io-backend = <&sd_adc0>;
+		};
+	};
+
+	dfsdm1: filter@1 {
+		compatible = "st,stm32-dfsdm-adc";
+		st,filter-order = <3>;
+		status = "okay";
+
+		channel@2 {
+			reg = <2>;
+			label = "in2";
+			st,adc-channel-types = "SPI_R";
+			st,adc-channel-clk-src = "CLKOUT";
+			io-backend = <&sd_adc1>;
+		};
+
+		channel@3 {
+			reg = <3>;
+			label = "in3";
+			st,adc-channel-types = "SPI_F";
+			st,adc-channel-clk-src = "CLKOUT";
+			io-backend = <&sd_adc2>;
+		};
+	};
+};
+
 &dsi {
 	phy-dsi-supply = <&reg18>;
 	status = "okay";