diff mbox series

[04/15] dt-bindings: clock: qcom,dispcc-sm6125: Allow power-domains property

Message ID 20230624-sm6125-dpu-v1-4-1d5a638cebf2@somainline.org
State New
Headers show
Series drm/msm: Add SM6125 MDSS/DPU hardware and enable Sony Xperia 10 II panel | expand

Commit Message

Marijn Suijten June 24, 2023, 12:41 a.m. UTC 
On SM6125 the dispcc block is gated behind VDDCX: allow this domain to
be configured.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
 Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 5 +++++
 1 file changed, 5 insertions(+)
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
index 11ec154503a3..02796675e8f6 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
@@ -46,6 +46,9 @@  properties:
   '#power-domain-cells':
     const: 1
 
+  power-domains:
+    maxItems: 1
+
   reg:
     maxItems: 1
 
@@ -63,6 +66,7 @@  examples:
   - |
     #include <dt-bindings/clock/qcom,rpmcc.h>
     #include <dt-bindings/clock/qcom,gcc-sm6125.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
     clock-controller@5f00000 {
       compatible = "qcom,sm6125-dispcc";
       reg = <0x5f00000 0x20000>;
@@ -80,6 +84,7 @@  examples:
                     "dsi1_phy_pll_out_dsiclk",
                     "dp_phy_pll_link_clk",
                     "dp_phy_pll_vco_div_clk";
+      power-domains = <&rpmpd SM6125_VDDCX>;
       #clock-cells = <1>;
       #power-domain-cells = <1>;
     };