Message ID | 1687433656-7892-8-git-send-email-spujar@nvidia.com |
---|---|
State | Superseded |
Headers | show |
Series | Few audio fixes on Tegra platforms | expand |
On 22-06-2023 17:43, Mark Brown wrote: > On Thu, Jun 22, 2023 at 05:04:15PM +0530, Sameer Pujar wrote: >> From: Sheetal <sheetal@nvidia.com> >> >> I2S data sanity tests fail beyond a bit clock frequency of 6.144MHz. >> This happens because the AHUB clock rate is too low and it shows >> 9.83MHz on boot. >> >> The maximum rate of PLLA_OUT0 is 49.152MHz and is used to serve I/O >> clocks. It is recommended that AHUB clock operates higher than this. >> Thus fix this by using PLLP_OUT0 as parent clock for AHUB instead of >> PLLA_OUT0 and fix the rate to 81.6MHz. >> >> Fixes: dc94a94daa39 ("arm64: tegra: Add audio devices on Tegra234") >> Cc: stable@vger.kernel.org >> Signed-off-by: Sheetal <sheetal@nvidia.com> > Fixes should come before cleanups in a patch series to ensure that they > can be applied and sent as fixes without dependencies on non-fixes. I sorted the series based on the subsystem. Will make sure to put 'fixes' patch always first. Thanks.
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f4974e8..0f12a8de 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -180,7 +180,8 @@ clocks = <&bpmp TEGRA234_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; - assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clock-rates = <81600000>; status = "disabled"; #address-cells = <2>;