| Message ID | ZJC3eK8QMxShyZDt@lenoch |
|---|---|
| State | New |
| Headers | show |
| Series | [01/11] MIPS: OCTEON: octeon-usb: add all register offsets | expand |
On Mon, Jun 19, 2023, Ladislav Michl wrote: > From: Ladislav Michl <ladis@linux-mips.org> > > Make dwc3_octeon_clocks_start just start the clocks. > > Signed-off-by: Ladislav Michl <ladis@linux-mips.org> > --- > drivers/usb/dwc3/dwc3-octeon.c | 150 ++++++++++++++++----------------- > 1 file changed, 71 insertions(+), 79 deletions(-) > > diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c > index 3ebcf2a61233..4ad2d8887cf0 100644 > --- a/drivers/usb/dwc3/dwc3-octeon.c > +++ b/drivers/usb/dwc3/dwc3-octeon.c > @@ -295,67 +295,14 @@ static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) > return 0; > } > > -static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) > +static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base, > + int ref_clk_sel, int ref_clk_fsel, > + int mpll_mul) > { > - int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; > - u32 clock_rate; > + int div; > u64 val; > void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; > > - if (dev->of_node) { > - const char *ss_clock_type; > - const char *hs_clock_type; > - > - i = of_property_read_u32(dev->of_node, > - "refclk-frequency", &clock_rate); > - if (i) { > - dev_err(dev, "No UCTL \"refclk-frequency\"\n"); > - return -EINVAL; > - } > - i = of_property_read_string(dev->of_node, > - "refclk-type-ss", &ss_clock_type); > - if (i) { > - dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); > - return -EINVAL; > - } > - i = of_property_read_string(dev->of_node, > - "refclk-type-hs", &hs_clock_type); > - if (i) { > - dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); > - return -EINVAL; > - } > - if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { > - if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) > - ref_clk_sel = 0; > - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) > - ref_clk_sel = 2; > - else > - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", > - hs_clock_type); > - } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { > - if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) > - ref_clk_sel = 1; > - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) > - ref_clk_sel = 3; > - else { > - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", > - hs_clock_type); > - ref_clk_sel = 3; > - } > - } else > - dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", > - ss_clock_type); > - > - if ((ref_clk_sel == 0 || ref_clk_sel == 1) && > - (clock_rate != 100000000)) > - dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n", > - clock_rate); > - > - } else { > - dev_err(dev, "No USB UCTL device node\n"); > - return -EINVAL; > - } > - > /* > * Step 1: Wait for all voltages to be stable...that surely > * happened before starting the kernel. SKIP > @@ -399,24 +346,6 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) > val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; > val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); > > - ref_clk_fsel = 0x07; > - switch (clock_rate) { > - default: > - dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", > - clock_rate); > - fallthrough; > - case 100000000: > - mpll_mul = 0x19; > - if (ref_clk_sel < 2) > - ref_clk_fsel = 0x27; > - break; > - case 50000000: > - mpll_mul = 0x32; > - break; > - case 125000000: > - mpll_mul = 0x28; > - break; > - } > val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL; > val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel); > > @@ -502,8 +429,72 @@ static void __init dwc3_octeon_phy_reset(void __iomem *base) > static int dwc3_octeon_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > + struct device_node *node = dev->of_node; > struct dwc3_data *data; > - int err; > + int err, ref_clk_sel, ref_clk_fsel, mpll_mul; > + uint32_t clock_rate; > + const char *hs_clock_type, *ss_clock_type; > + > + if (!node) { > + dev_err(dev, "No USB UCTL device node\n"); > + return -EINVAL; > + } > + > + if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) { > + dev_err(dev, "No UCTL \"refclk-frequency\"\n"); > + return -EINVAL; > + } > + if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) { > + dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); > + return -EINVAL; > + } > + if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) { > + dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); > + return -EINVAL; > + } > + > + ref_clk_sel = 2; Can we use macro instead of magic numbers? > + if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { > + if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) > + ref_clk_sel = 0; > + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) > + ref_clk_sel = 2; > + else > + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", > + hs_clock_type); > + } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { > + if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) > + ref_clk_sel = 1; > + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) > + ref_clk_sel = 3; Please run checkpatch and fix minor formatting issues such as bracket here. > + else { > + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", > + hs_clock_type); > + ref_clk_sel = 3; > + } > + } else { > + dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", > + ss_clock_type); > + } > + > + ref_clk_fsel = 0x07; > + switch (clock_rate) { > + default: > + dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", > + clock_rate); > + fallthrough; > + case 100000000: > + mpll_mul = 0x19; > + if (ref_clk_sel < 2) > + ref_clk_fsel = 0x27; > + break; > + case 50000000: > + mpll_mul = 0x32; > + break; > + case 125000000: > + mpll_mul = 0x28; > + break; > + } > > data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); > if (!data) > @@ -516,7 +507,8 @@ static int dwc3_octeon_probe(struct platform_device *pdev) > if (IS_ERR(data->base)) > return PTR_ERR(data->base); > > - err = dwc3_octeon_clocks_start(dev, data->base); > + err = dwc3_octeon_clocks_start(dev, data->base, > + ref_clk_sel, ref_clk_fsel, mpll_mul); > if (err) > return err; > > -- > 2.39.2 > Thanks, Thinh
On Sun, Jul 02, 2023, Ladislav Michl wrote: > Hi, > > thank you for review, v2 is about to be sent, here just let > me anwer issue I didn't address there. > > On Fri, Jun 30, 2023 at 11:27:37PM +0000, Thinh Nguyen wrote: > > On Mon, Jun 19, 2023, Ladislav Michl wrote: > [snip] > > > + ref_clk_sel = 2; > > > > Can we use macro instead of magic numbers? > > This is a bit problematic, comment above USBDRD_UCTL_CTL_REF_CLK_SEL > says: > /* Reference clock select for SuperSpeed and HighSpeed PLLs: > * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock > * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock > * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock & > * HighSpeed PLL uses PLL_REF_CLK for reference clck > * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock & > * HighSpeed PLL uses PLL_REF_CLK for reference clck > */ > So I really cannot imagine sane name. Also please note, that field > and register names were created to match documentation. Values, > however, have no defined names, so I would need to invent them. > That is something I'd like to avoid as it might be confusing. > > And last, but to least: Octeon would deserve proper clock api > (clk driver to be implemented). So hopefully that code get > replaced with more sane one. For now, I just kept compatibility > with current DT. > > Thanks, > ladis Sure. That's reasonable. Thanks, Thinh
diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 3ebcf2a61233..4ad2d8887cf0 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -295,67 +295,14 @@ static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) return 0; } -static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) +static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base, + int ref_clk_sel, int ref_clk_fsel, + int mpll_mul) { - int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; - u32 clock_rate; + int div; u64 val; void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; - if (dev->of_node) { - const char *ss_clock_type; - const char *hs_clock_type; - - i = of_property_read_u32(dev->of_node, - "refclk-frequency", &clock_rate); - if (i) { - dev_err(dev, "No UCTL \"refclk-frequency\"\n"); - return -EINVAL; - } - i = of_property_read_string(dev->of_node, - "refclk-type-ss", &ss_clock_type); - if (i) { - dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); - return -EINVAL; - } - i = of_property_read_string(dev->of_node, - "refclk-type-hs", &hs_clock_type); - if (i) { - dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); - return -EINVAL; - } - if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { - if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) - ref_clk_sel = 0; - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) - ref_clk_sel = 2; - else - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", - hs_clock_type); - } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { - if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) - ref_clk_sel = 1; - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) - ref_clk_sel = 3; - else { - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", - hs_clock_type); - ref_clk_sel = 3; - } - } else - dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", - ss_clock_type); - - if ((ref_clk_sel == 0 || ref_clk_sel == 1) && - (clock_rate != 100000000)) - dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n", - clock_rate); - - } else { - dev_err(dev, "No USB UCTL device node\n"); - return -EINVAL; - } - /* * Step 1: Wait for all voltages to be stable...that surely * happened before starting the kernel. SKIP @@ -399,24 +346,6 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); - ref_clk_fsel = 0x07; - switch (clock_rate) { - default: - dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", - clock_rate); - fallthrough; - case 100000000: - mpll_mul = 0x19; - if (ref_clk_sel < 2) - ref_clk_fsel = 0x27; - break; - case 50000000: - mpll_mul = 0x32; - break; - case 125000000: - mpll_mul = 0x28; - break; - } val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel); @@ -502,8 +429,72 @@ static void __init dwc3_octeon_phy_reset(void __iomem *base) static int dwc3_octeon_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; struct dwc3_data *data; - int err; + int err, ref_clk_sel, ref_clk_fsel, mpll_mul; + uint32_t clock_rate; + const char *hs_clock_type, *ss_clock_type; + + if (!node) { + dev_err(dev, "No USB UCTL device node\n"); + return -EINVAL; + } + + if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) { + dev_err(dev, "No UCTL \"refclk-frequency\"\n"); + return -EINVAL; + } + if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) { + dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); + return -EINVAL; + } + if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) { + dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); + return -EINVAL; + } + + ref_clk_sel = 2; + if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) + ref_clk_sel = 0; + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) + ref_clk_sel = 2; + else + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) + ref_clk_sel = 1; + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) + ref_clk_sel = 3; + else { + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + ref_clk_sel = 3; + } + } else { + dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", + ss_clock_type); + } + + ref_clk_fsel = 0x07; + switch (clock_rate) { + default: + dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", + clock_rate); + fallthrough; + case 100000000: + mpll_mul = 0x19; + if (ref_clk_sel < 2) + ref_clk_fsel = 0x27; + break; + case 50000000: + mpll_mul = 0x32; + break; + case 125000000: + mpll_mul = 0x28; + break; + } data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) @@ -516,7 +507,8 @@ static int dwc3_octeon_probe(struct platform_device *pdev) if (IS_ERR(data->base)) return PTR_ERR(data->base); - err = dwc3_octeon_clocks_start(dev, data->base); + err = dwc3_octeon_clocks_start(dev, data->base, + ref_clk_sel, ref_clk_fsel, mpll_mul); if (err) return err;