| Message ID | 20230614092850.21460-5-stanley_chang@realtek.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v4,1/5] usb: phy: add usb phy notify port status API | expand |
On 14/06/2023 11:28, Stanley Chang wrote: > Add the documentation explain the property about Realtek USB PHY driver. > > Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB > controller. Added the driver to drive the USB 3.0 PHY transceivers. > > Signed-off-by: Stanley Chang <stanley_chang@realtek.com> > --- > v3 to v4 change: > 1. Remove the parameter and non hardware properties from dts. > 2. Using the compatible data included the config and parameter > in driver. > v2 to v3 change: > 1. Broken down into two patches, one for each of USB 2 & 3. > 2. Add more description about Realtek RTD SoCs architecture. > 3. Removed parameter v1 support for simplification. > 4. Revised the compatible name for fallback compatible. > 5. Remove some properties that can be set in the driver. > v1 to v2 change: > Add phy-cells for generic phy driver > --- > .../bindings/phy/realtek,usb3phy.yaml | 105 ++++++++++++++++++ > 1 file changed, 105 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml b/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml > new file mode 100644 > index 000000000000..0f849cf942e8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright 2023 Realtek Semiconductor Corporation > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/realtek,usb3phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Realtek DHC SoCs USB 3.0 PHY > + > +maintainers: > + - Stanley Chang <stanley_chang@realtek.com> > + > +description: > + Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs. > + The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs > + support multiple XHCI controllers. One PHY device node maps to one XHCI > + controller. > + > + RTD1295/RTD1619 SoCs USB > + The USB architecture includes three XHCI controllers. > + Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some > + controllers. > + XHCI controller#0 -- usb2phy -- phy#0 > + |- usb3phy -- phy#0 > + XHCI controller#1 -- usb2phy -- phy#0 > + XHCI controller#2 -- usb2phy -- phy#0 > + |- usb3phy -- phy#0 > + > + RTD1319/RTD1619b SoCs USB > + The USB architecture includes three XHCI controllers. > + Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2. > + XHCI controller#0 -- usb2phy -- phy#0 > + XHCI controller#1 -- usb2phy -- phy#0 > + XHCI controller#2 -- usb2phy -- phy#0 > + |- usb3phy -- phy#0 > + > + RTD1319d SoCs USB > + The USB architecture includes three XHCI controllers. > + Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0. > + XHCI controller#0 -- usb2phy -- phy#0 > + |- usb3phy -- phy#0 > + XHCI controller#1 -- usb2phy -- phy#0 > + XHCI controller#2 -- usb2phy -- phy#0 > + > +properties: > + compatible: > + items: > + - enum: > + - realtek,rtd1295-usb3phy > + - realtek,rtd1319-usb3phy > + - realtek,rtd1319d-usb3phy > + - realtek,rtd1619-usb3phy > + - realtek,rtd1619b-usb3phy > + - const: realtek,usb3phy Drop last compatible, it is not used now. Does not make sense. > + > + reg: > + description: PHY data registers Drop description, it's obvious. > + maxItems: 1 > + > + "#phy-cells": > + const: 0 > + > + nvmem-cells: > + maxItems: 1 > + description: A phandle to the tx lfps swing trim data provided by > + a nvmem device, if unspecified, default values shall be used. > + > + nvmem-cell-names: > + items: > + - const: usb_u3_tx_lfps_swing_trim > + > + realtek,amplitude-control-coarse-tuning: > + description: > + This adjusts the signal amplitude for normal operation and beacon LFPS. > + This value is a parameter for coarse tuning. > + For different boards, if the default value is inappropriate, this > + property can be assigned to adjust. default: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 255 > + > + realtek,amplitude-control-fine-tuning: > + description: > + This adjusts the signal amplitude for normal operation and beacon LFPS. > + This value is used for fine-tuning parameters. > + $ref: /schemas/types.yaml#/definitions/uint32 default: > + minimum: 0 > + maximum: 65535 > + Best regards, Krzysztof
Hi Krzysztof, > > +properties: > > + compatible: > > + items: > > + - enum: > > + - realtek,rtd1295-usb3phy > > + - realtek,rtd1319-usb3phy > > + - realtek,rtd1319d-usb3phy > > + - realtek,rtd1619-usb3phy > > + - realtek,rtd1619b-usb3phy > > + - const: realtek,usb3phy > > Drop last compatible, it is not used now. Does not make sense. Okay. I will remove it. > > + > > + reg: > > + description: PHY data registers > > Drop description, it's obvious. Okay. > > + maxItems: 1 > > + > > + "#phy-cells": > > + const: 0 > > + > > + nvmem-cells: > > + maxItems: 1 > > + description: A phandle to the tx lfps swing trim data provided by > > + a nvmem device, if unspecified, default values shall be used. > > + > > + nvmem-cell-names: > > + items: > > + - const: usb_u3_tx_lfps_swing_trim > > + > > + realtek,amplitude-control-coarse-tuning: > > + description: > > + This adjusts the signal amplitude for normal operation and beacon > LFPS. > > + This value is a parameter for coarse tuning. > > + For different boards, if the default value is inappropriate, this > > + property can be assigned to adjust. > > default: I will add it. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 0 > > + maximum: 255 > > + > > + realtek,amplitude-control-fine-tuning: > > + description: > > + This adjusts the signal amplitude for normal operation and beacon > LFPS. > > + This value is used for fine-tuning parameters. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > default: I will add it. > > + minimum: 0 > > + maximum: 65535 > > + > Thanks, Stanley
diff --git a/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml b/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml new file mode 100644 index 000000000000..0f849cf942e8 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/realtek,usb3phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC SoCs USB 3.0 PHY + +maintainers: + - Stanley Chang <stanley_chang@realtek.com> + +description: + Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs. + The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs + support multiple XHCI controllers. One PHY device node maps to one XHCI + controller. + + RTD1295/RTD1619 SoCs USB + The USB architecture includes three XHCI controllers. + Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some + controllers. + XHCI controller#0 -- usb2phy -- phy#0 + |- usb3phy -- phy#0 + XHCI controller#1 -- usb2phy -- phy#0 + XHCI controller#2 -- usb2phy -- phy#0 + |- usb3phy -- phy#0 + + RTD1319/RTD1619b SoCs USB + The USB architecture includes three XHCI controllers. + Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2. + XHCI controller#0 -- usb2phy -- phy#0 + XHCI controller#1 -- usb2phy -- phy#0 + XHCI controller#2 -- usb2phy -- phy#0 + |- usb3phy -- phy#0 + + RTD1319d SoCs USB + The USB architecture includes three XHCI controllers. + Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0. + XHCI controller#0 -- usb2phy -- phy#0 + |- usb3phy -- phy#0 + XHCI controller#1 -- usb2phy -- phy#0 + XHCI controller#2 -- usb2phy -- phy#0 + +properties: + compatible: + items: + - enum: + - realtek,rtd1295-usb3phy + - realtek,rtd1319-usb3phy + - realtek,rtd1319d-usb3phy + - realtek,rtd1619-usb3phy + - realtek,rtd1619b-usb3phy + - const: realtek,usb3phy + + reg: + description: PHY data registers + maxItems: 1 + + "#phy-cells": + const: 0 + + nvmem-cells: + maxItems: 1 + description: A phandle to the tx lfps swing trim data provided by + a nvmem device, if unspecified, default values shall be used. + + nvmem-cell-names: + items: + - const: usb_u3_tx_lfps_swing_trim + + realtek,amplitude-control-coarse-tuning: + description: + This adjusts the signal amplitude for normal operation and beacon LFPS. + This value is a parameter for coarse tuning. + For different boards, if the default value is inappropriate, this + property can be assigned to adjust. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + + realtek,amplitude-control-fine-tuning: + description: + This adjusts the signal amplitude for normal operation and beacon LFPS. + This value is used for fine-tuning parameters. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 65535 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + usb_port2_usb3phy: usb-phy@13e10 { + compatible = "realtek,rtd1319d-usb3phy", "realtek,usb3phy"; + reg = <0x13e10 0x4>; + #phy-cells = <0>; + + realtek,amplitude-control-coarse-tuning = <0x77>; + };
Add the documentation explain the property about Realtek USB PHY driver. Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB controller. Added the driver to drive the USB 3.0 PHY transceivers. Signed-off-by: Stanley Chang <stanley_chang@realtek.com> --- v3 to v4 change: 1. Remove the parameter and non hardware properties from dts. 2. Using the compatible data included the config and parameter in driver. v2 to v3 change: 1. Broken down into two patches, one for each of USB 2 & 3. 2. Add more description about Realtek RTD SoCs architecture. 3. Removed parameter v1 support for simplification. 4. Revised the compatible name for fallback compatible. 5. Remove some properties that can be set in the driver. v1 to v2 change: Add phy-cells for generic phy driver --- .../bindings/phy/realtek,usb3phy.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml