diff mbox

[v2,00/22] GICv3 emulation

Message ID 20160530111509.hvjswcrxbwaq24u6@hawk.localdomain
State New
Headers show

Commit Message

Andrew Jones May 30, 2016, 11:15 a.m. UTC 
On Thu, May 26, 2016 at 03:55:18PM +0100, Peter Maydell wrote:
> This series implements emulation of the GICv3 interrupt controller.

> It is based to some extent on previous patches from Shlomo and

> Pavel, but the bulk of it has turned out to be new code. (The

> combination of changing the underlying data structures, adding

> support for TrustZone and implementing proper GICv3 behaviour rather

> than borrowing fragments of GICv2 emulation code meant there wasn't

> much left to reuse.) I've tried to reflect this in the various

> authorship credits on the patches, but please let me know if you

> feel I got anything miscredited one way or the other.

> 

> Key points about the GICv3 emulated here:

>  * "non-legacy" only, ie system registers and affinity routing

>  * TrustZone is implemented

>  * no virtualization support

>  * only the "core" GICv3, so no LPI support (via ITS or otherwise)

>  * no attempt to work around the Linux guest kernel bug fixed

>    in commit 7c9b973061b0 (so you need that fix for your guest to

>    boot with this GICv3)

> 

> I have included the "support KVM save/restore" patches from Pavel,

> reworked to use the new data structures, but they are only RFC

> status because the kernel API is not yet final (there are a couple

> of loose threads there to be followed up). Those patches are at the

> end of the series; I think everything else is in a commitable state

> (give or take code review).

> 

> Testing: I have confirmed that we can boot a Linux guest kernel,

> but not tried any other GIC-using guest code. I've done some light

> stress-testing using 'stress', and checked an SMP (2-cpu) boot.

> I've also tested booting a guest kernel via UEFI.

> 

> Design: all the code here is in hw/intc/, split into several

> files to avoid them being huge. The interface between the CPU

> proper and the CPU interface is a bit ad-hoc (you can see the

> awkward seams that result from the choice to think of the cpu

> i/f as part of the GIC device rather than part of the CPU itself),

> but I think that if you put the cpu i/f in the CPU you'd end up

> with an ad-hoc interface and awkward seams in the other direction.

> The GICv3 device currently assumes it is always connected to all

> CPUs; we can change that later to allow some kind of QOM link

> property to specify the CPUs explicitly, but I think this is OK

> for now (and it's already a pretty huge set of code changes to

> have to review).

> 

> Code review, testing, attempts to run guests other than Linux

> welcome.

> 

> Changes v1->v2:

>  * I have dropped the kernel bug workaround, since it didn't work for

>    boots via UEFI anyway. This means that you will need kernel commit

>    7c9b973061b0 (or its equivalent backports to stable) to boot a Linux

>    guest with this emulated GICv3

>  * make bitmaps and arrays be GIC_MAXIRQS in size rather than

>    GIC_MAXSPIS in size; this uses an extra 512 bytes or so per

>    vcpu, but makes bugs of the "forgot to add/subtract GIC_INTERNAL"

>    variety less likely to happen (and indeed a few were found and fixed

>    in making this change...)

>  * fixed GICD_CTLR NS read to use correct bitmask

>  * moved ARMELChangeHook related prototypes etc into cpu.h from cpu-qom.h

>    (needed after Paolo's recent header reshuffles)

>  * added missing 'inline' qualifier to arm_is_el3_or_mon()

>  * fixed missing reset of GICD_NSACR

>  * fixed icc_activate_irq() to call gicv3_redist_update() rather than

>    gicv3_update() when it changes redistributor state

>  * make sure (and assert) gicv3_update() isn't called for out of range irqs

>  * add missing "bad num_irqs values" checks from gicv2 code


I've lightly tested this with kvm-unit-tests (I say lightly, because
it only does IPI testing so far). Although I did try with 123 vcpus,
the max mach-virt currently supports. I'm not sure the testing is
enough to warrant any tested-by's. I mostly just advertising the
unit test, which is here
https://github.com/rhdrjones/kvm-unit-tests/commits/arm/gic

Also, below is a follow-on patch for mach-virt, which might be
of interest.

Thanks,
drew


From: Andrew Jones <drjones@redhat.com>

Date: Mon, 30 May 2016 12:58:26 +0200
Subject: [PATCH] hw/arm/virt: gicv3: use all target-list bits

Signed-off-by: Andrew Jones <drjones@redhat.com>

---
 hw/arm/virt.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

-- 
2.4.11
diff mbox

Patch

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e77ed88afb8a2..753c9ff8ccd64 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1204,6 +1204,16 @@  static void machvirt_init(MachineState *machine)
         }
         cpuobj = object_new(object_class_get_name(oc));
 
+        /* Adjust MPIDR per the GIC's target-list size. */
+        if (gic_version == 3) {
+            CPUState *cs = CPU(cpuobj);
+            uint8_t Aff1 = cs->cpu_index / 16;
+            uint8_t Aff0 = cs->cpu_index % 16;
+
+            object_property_set_int(cpuobj, (Aff1 << ARM_AFF1_SHIFT) | Aff0,
+                                    "mp-affinity", NULL);
+        }
+
         /* Handle any CPU options specified by the user */
         cc->parse_features(CPU(cpuobj), cpuopts, &err);
         g_free(cpuopts);