diff mbox series

[04/20] target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree

Message ID 20230602155223.2040685-5-peter.maydell@linaro.org
State Superseded
Headers show
Series target/arm: Convert exception, system, loads and stores to decodetree | expand

Commit Message

Peter Maydell June 2, 2023, 3:52 p.m. UTC 
Convert the CFINV, XAFLAG and AXFLAG insns to decodetree.
The old decoder handles these in handle_msr_i(), but
the architecture defines them as separate instructions
from MSR (immediate).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/a64.decode      |  6 ++++
 target/arm/tcg/translate-a64.c | 56 ++++++++++++++++++----------------
 2 files changed, 35 insertions(+), 27 deletions(-)

Comments

Richard Henderson June 3, 2023, 5:55 a.m. UTC | #1 
On 6/2/23 08:52, Peter Maydell wrote:
> Convert the CFINV, XAFLAG and AXFLAG insns to decodetree.
> The old decoder handles these in handle_msr_i(), but
> the architecture defines them as separate instructions
> from MSR (immediate).
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/arm/tcg/a64.decode      |  6 ++++
>   target/arm/tcg/translate-a64.c | 56 ++++++++++++++++++----------------
>   2 files changed, 35 insertions(+), 27 deletions(-)
> 
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index 553f6904d9c..26a0b44cea9 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -188,3 +188,9 @@ CLREX           1101 0101 0000 0011 0011 imm:4 010 11111
>   DSB_DMB         1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
>   ISB             1101 0101 0000 0011 0011 imm:4 110 11111
>   SB              1101 0101 0000 0011 0011 0000 111 11111
> +
> +# PSTATE
> +
> +CFINV           1101 0101 0000 0 000 0100 0000 000 11111
> +XAFLAG          1101 0101 0000 0 000 0100 0000 001 11111
> +AXFLAG          1101 0101 0000 0 000 0100 0000 010 11111
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 09258a9854f..33bebe594d1 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -1809,9 +1809,25 @@ static bool trans_SB(DisasContext *s, arg_SB *a)
>       return true;
>   }
>   
> -static void gen_xaflag(void)
> +static bool trans_CFINV(DisasContext *s, arg_CFINV *a)
>   {
> -    TCGv_i32 z = tcg_temp_new_i32();
> +    if (!dc_isar_feature(aa64_condm_4, s)) {
> +        return false;
> +    }
> +    tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);
> +    s->base.is_jmp = DISAS_NEXT;
> +    return true;
> +}

The settings of is_jmp do not need to be copied across.
That's another benefit of extracting from MSR_i.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox series

Patch

diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 553f6904d9c..26a0b44cea9 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -188,3 +188,9 @@  CLREX           1101 0101 0000 0011 0011 imm:4 010 11111
 DSB_DMB         1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
 ISB             1101 0101 0000 0011 0011 imm:4 110 11111
 SB              1101 0101 0000 0011 0011 0000 111 11111
+
+# PSTATE
+
+CFINV           1101 0101 0000 0 000 0100 0000 000 11111
+XAFLAG          1101 0101 0000 0 000 0100 0000 001 11111
+AXFLAG          1101 0101 0000 0 000 0100 0000 010 11111
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 09258a9854f..33bebe594d1 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1809,9 +1809,25 @@  static bool trans_SB(DisasContext *s, arg_SB *a)
     return true;
 }
 
-static void gen_xaflag(void)
+static bool trans_CFINV(DisasContext *s, arg_CFINV *a)
 {
-    TCGv_i32 z = tcg_temp_new_i32();
+    if (!dc_isar_feature(aa64_condm_4, s)) {
+        return false;
+    }
+    tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);
+    s->base.is_jmp = DISAS_NEXT;
+    return true;
+}
+
+static bool trans_XAFLAG(DisasContext *s, arg_XAFLAG *a)
+{
+    TCGv_i32 z;
+
+    if (!dc_isar_feature(aa64_condm_5, s)) {
+        return false;
+    }
+
+    z = tcg_temp_new_i32();
 
     tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0);
 
@@ -1835,10 +1851,17 @@  static void gen_xaflag(void)
 
     /* C | Z */
     tcg_gen_or_i32(cpu_CF, cpu_CF, z);
+
+    s->base.is_jmp = DISAS_NEXT;
+    return true;
 }
 
-static void gen_axflag(void)
+static bool trans_AXFLAG(DisasContext *s, arg_AXFLAG *a)
 {
+    if (!dc_isar_feature(aa64_condm_5, s)) {
+        return false;
+    }
+
     tcg_gen_sari_i32(cpu_VF, cpu_VF, 31);         /* V ? -1 : 0 */
     tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF);     /* C & !V */
 
@@ -1847,6 +1870,9 @@  static void gen_axflag(void)
 
     tcg_gen_movi_i32(cpu_NF, 0);
     tcg_gen_movi_i32(cpu_VF, 0);
+
+    s->base.is_jmp = DISAS_NEXT;
+    return true;
 }
 
 /* MSR (immediate) - move immediate to processor state field */
@@ -1859,30 +1885,6 @@  static void handle_msr_i(DisasContext *s, uint32_t insn,
     s->base.is_jmp = DISAS_TOO_MANY;
 
     switch (op) {
-    case 0x00: /* CFINV */
-        if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) {
-            goto do_unallocated;
-        }
-        tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);
-        s->base.is_jmp = DISAS_NEXT;
-        break;
-
-    case 0x01: /* XAFlag */
-        if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
-            goto do_unallocated;
-        }
-        gen_xaflag();
-        s->base.is_jmp = DISAS_NEXT;
-        break;
-
-    case 0x02: /* AXFlag */
-        if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
-            goto do_unallocated;
-        }
-        gen_axflag();
-        s->base.is_jmp = DISAS_NEXT;
-        break;
-
     case 0x03: /* UAO */
         if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) {
             goto do_unallocated;