diff mbox series

[V1,1/1] mmc: sdhci: fix DMA configure compatibility issue when 64bit DMA mode is used.

Message ID 20230523111114.18124-1-chevron_li@126.com
State New
Headers show
Series [V1,1/1] mmc: sdhci: fix DMA configure compatibility issue when 64bit DMA mode is used. | expand

Commit Message

Chevron Li May 23, 2023, 11:11 a.m. UTC 
From: Chevron Li <chevron.li@bayhubtech.com>

Bayhub SD host has hardware limitation:
1.The upper 32bit address is inhibited to be written at SD Host Register
  [03E][13]=0 (32bits addressing) mode, is admitted to be written only at
  SD Host Register [03E][13]=1 (64bits addressing) mode.
2.Because of above item#1, need to configure SD Host Register [03E][13] to
  1(64bits addressing mode) before set 64bit ADMA system address's higher
  32bits SD Host Register [05F~05C] if 64 bits addressing mode is used.

The hardware limitation is reasonable for below reasons:
1.Normal flow should set DMA working mode first, then do
  DMA-transfer-related configuration, such as system address.
2.The hardware limitation may avoid the software to configure wrong higher
  32bit address at 32bits addressing mode although it is redundant.

The change that set 32bits/64bits addressing mode before set ADMA address,
  has no side-effect to other host IPs for below reason:
The setting order is reasonable and standard: DMA Mode setting first and
  then DMA address setting. It meets all DMA setting sequence.

Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>
---
Change in V1:
Set dma mode configure before set dma address
---
 drivers/mmc/host/sdhci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


base-commit: cc3c44c9fda264c6d401be04e95449a57c1231c6

Comments

Chevron Li (WH) May 29, 2023, 12:07 p.m. UTC | #1 
Hi, Adrian/Ulf,

May I know the patch progress?
Look forward your response.

BR,
Chevron

-----Original Message-----
From: Chevron Li <chevron_li@126.com> 
Sent: Tuesday, May 23, 2023 19:11
To: adrian.hunter@intel.com; ulf.hansson@linaro.org; linux-mmc@vger.kernel.org; linux-kernel@vger.kernel.org
Cc: Shirley Her(SC) <shirley.her@bayhubtech.com>; XiaoGuang Yu (WH) <xiaoguang.yu@bayhubtech.com>; Shaper Liu (WH) <shaper.liu@bayhubtech.com>; Justin Wang (WH) <justin.wang@bayhubtech.com>; Chevron Li (WH) <chevron.li@bayhubtech.com>
Subject: [PATCH V1 1/1] mmc: sdhci: fix DMA configure compatibility issue when 64bit DMA mode is used.

From: Chevron Li <chevron.li@bayhubtech.com>

Bayhub SD host has hardware limitation:
1.The upper 32bit address is inhibited to be written at SD Host Register
  [03E][13]=0 (32bits addressing) mode, is admitted to be written only at
  SD Host Register [03E][13]=1 (64bits addressing) mode.
2.Because of above item#1, need to configure SD Host Register [03E][13] to
  1(64bits addressing mode) before set 64bit ADMA system address's higher
  32bits SD Host Register [05F~05C] if 64 bits addressing mode is used.

The hardware limitation is reasonable for below reasons:
1.Normal flow should set DMA working mode first, then do
  DMA-transfer-related configuration, such as system address.
2.The hardware limitation may avoid the software to configure wrong higher
  32bit address at 32bits addressing mode although it is redundant.

The change that set 32bits/64bits addressing mode before set ADMA address,
  has no side-effect to other host IPs for below reason:
The setting order is reasonable and standard: DMA Mode setting first and
  then DMA address setting. It meets all DMA setting sequence.

Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>
---
Change in V1:
Set dma mode configure before set dma address
---
 drivers/mmc/host/sdhci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 3241916141d7..ff41aa56564e 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1167,6 +1167,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 		}
 	}
 
+	sdhci_config_dma(host);
+
 	if (host->flags & SDHCI_REQ_USE_DMA) {
 		int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
 
@@ -1186,8 +1188,6 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 		}
 	}
 
-	sdhci_config_dma(host);
-
 	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 		int flags;
 

base-commit: cc3c44c9fda264c6d401be04e95449a57c1231c6
--
2.25.1
Adrian Hunter May 29, 2023, 3 p.m. UTC | #2 
On 23/05/23 14:11, Chevron Li wrote:
> From: Chevron Li <chevron.li@bayhubtech.com>
> 
> Bayhub SD host has hardware limitation:
> 1.The upper 32bit address is inhibited to be written at SD Host Register
>   [03E][13]=0 (32bits addressing) mode, is admitted to be written only at
>   SD Host Register [03E][13]=1 (64bits addressing) mode.
> 2.Because of above item#1, need to configure SD Host Register [03E][13] to
>   1(64bits addressing mode) before set 64bit ADMA system address's higher
>   32bits SD Host Register [05F~05C] if 64 bits addressing mode is used.
> 
> The hardware limitation is reasonable for below reasons:
> 1.Normal flow should set DMA working mode first, then do
>   DMA-transfer-related configuration, such as system address.
> 2.The hardware limitation may avoid the software to configure wrong higher
>   32bit address at 32bits addressing mode although it is redundant.
> 
> The change that set 32bits/64bits addressing mode before set ADMA address,
>   has no side-effect to other host IPs for below reason:
> The setting order is reasonable and standard: DMA Mode setting first and
>   then DMA address setting. It meets all DMA setting sequence.
> 
> Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>

It should be OK.

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
> Change in V1:
> Set dma mode configure before set dma address
> ---
>  drivers/mmc/host/sdhci.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 3241916141d7..ff41aa56564e 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1167,6 +1167,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
>  		}
>  	}
>  
> +	sdhci_config_dma(host);
> +
>  	if (host->flags & SDHCI_REQ_USE_DMA) {
>  		int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
>  
> @@ -1186,8 +1188,6 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
>  		}
>  	}
>  
> -	sdhci_config_dma(host);
> -
>  	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
>  		int flags;
>  
> 
> base-commit: cc3c44c9fda264c6d401be04e95449a57c1231c6
Ulf Hansson June 8, 2023, 3:53 p.m. UTC | #3 
On Tue, 23 May 2023 at 13:12, Chevron Li <chevron_li@126.com> wrote:
>
> From: Chevron Li <chevron.li@bayhubtech.com>
>
> Bayhub SD host has hardware limitation:
> 1.The upper 32bit address is inhibited to be written at SD Host Register
>   [03E][13]=0 (32bits addressing) mode, is admitted to be written only at
>   SD Host Register [03E][13]=1 (64bits addressing) mode.
> 2.Because of above item#1, need to configure SD Host Register [03E][13] to
>   1(64bits addressing mode) before set 64bit ADMA system address's higher
>   32bits SD Host Register [05F~05C] if 64 bits addressing mode is used.
>
> The hardware limitation is reasonable for below reasons:
> 1.Normal flow should set DMA working mode first, then do
>   DMA-transfer-related configuration, such as system address.
> 2.The hardware limitation may avoid the software to configure wrong higher
>   32bit address at 32bits addressing mode although it is redundant.
>
> The change that set 32bits/64bits addressing mode before set ADMA address,
>   has no side-effect to other host IPs for below reason:
> The setting order is reasonable and standard: DMA Mode setting first and
>   then DMA address setting. It meets all DMA setting sequence.
>
> Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>

Applied for next, thanks!

Is this material for stable kernels too, as it fixes a real problem, no?

Kind regards
Uffe


> ---
> Change in V1:
> Set dma mode configure before set dma address
> ---
>  drivers/mmc/host/sdhci.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 3241916141d7..ff41aa56564e 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1167,6 +1167,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
>                 }
>         }
>
> +       sdhci_config_dma(host);
> +
>         if (host->flags & SDHCI_REQ_USE_DMA) {
>                 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
>
> @@ -1186,8 +1188,6 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
>                 }
>         }
>
> -       sdhci_config_dma(host);
> -
>         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
>                 int flags;
>
>
> base-commit: cc3c44c9fda264c6d401be04e95449a57c1231c6
> --
> 2.25.1
>
Ulf Hansson June 12, 2023, 2:16 p.m. UTC | #4 
On Fri, 9 Jun 2023 at 03:58, Chevron Li (WH) <chevron.li@bayhubtech.com> wrote:
>
> Hi, Ulf,
>
> Yes, this patch fixes a real problem.
>
> BR,
> Chevron
>
> > -----Original Message-----
> > From: Ulf Hansson <ulf.hansson@linaro.org>
> > Sent: Thursday, June 8, 2023 23:53
> > To: Chevron Li <chevron_li@126.com>
> > Cc: adrian.hunter@intel.com; linux-mmc@vger.kernel.org; linux-
> > kernel@vger.kernel.org; Shirley Her(SC) <shirley.her@bayhubtech.com>;
> > XiaoGuang Yu (WH) <xiaoguang.yu@bayhubtech.com>; Shaper Liu (WH)
> > <shaper.liu@bayhubtech.com>; Justin Wang (WH)
> > <justin.wang@bayhubtech.com>; Chevron Li (WH)
> > <chevron.li@bayhubtech.com>
> > Subject: Re: [PATCH V1 1/1] mmc: sdhci: fix DMA configure compatibility issue
> > when 64bit DMA mode is used.
> >
> > On Tue, 23 May 2023 at 13:12, Chevron Li <chevron_li@126.com> wrote:
> > >
> > > From: Chevron Li <chevron.li@bayhubtech.com>
> > >
> > > Bayhub SD host has hardware limitation:
> > > 1.The upper 32bit address is inhibited to be written at SD Host Register
> > >   [03E][13]=0 (32bits addressing) mode, is admitted to be written only at
> > >   SD Host Register [03E][13]=1 (64bits addressing) mode.
> > > 2.Because of above item#1, need to configure SD Host Register [03E][13] to
> > >   1(64bits addressing mode) before set 64bit ADMA system address's higher
> > >   32bits SD Host Register [05F~05C] if 64 bits addressing mode is used.
> > >
> > > The hardware limitation is reasonable for below reasons:
> > > 1.Normal flow should set DMA working mode first, then do
> > >   DMA-transfer-related configuration, such as system address.
> > > 2.The hardware limitation may avoid the software to configure wrong higher
> > >   32bit address at 32bits addressing mode although it is redundant.
> > >
> > > The change that set 32bits/64bits addressing mode before set ADMA
> > address,
> > >   has no side-effect to other host IPs for below reason:
> > > The setting order is reasonable and standard: DMA Mode setting first and
> > >   then DMA address setting. It meets all DMA setting sequence.
> > >
> > > Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>
> >
> > Applied for next, thanks!
> >
> > Is this material for stable kernels too, as it fixes a real problem, no?
> Yes, it fixes a real problem.

Okay, I have amended the patch by adding a stable tag to it!

[...]

Kind regards
Uffe
diff mbox series

Patch

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 3241916141d7..ff41aa56564e 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1167,6 +1167,8 @@  static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 		}
 	}
 
+	sdhci_config_dma(host);
+
 	if (host->flags & SDHCI_REQ_USE_DMA) {
 		int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
 
@@ -1186,8 +1188,6 @@  static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 		}
 	}
 
-	sdhci_config_dma(host);
-
 	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 		int flags;