| Message ID | 20230516154539.238655-1-krzysztof.kozlowski@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/3] arm64: dts: qcom: sm8550: enable DISPCC by default | expand |
On Tue, 16 May 2023 at 18:46, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > Enable the Display Clock Controller by default in SoC DTSI so unused > clocks can be turned off. It does not require any external resources, > so as core SoC component should be always available to boards. > > Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > Changes in v2: > 1. New patch > --- > arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 - > 2 files changed, 5 deletions(-)
On 16.05.2023 17:45, Krzysztof Kozlowski wrote: > Enable the Display Clock Controller by default in SoC DTSI so unused > clocks can be turned off. It does not require any external resources, > so as core SoC component should be always available to boards. > > Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > > Changes in v2: > 1. New patch > --- > arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 - > 2 files changed, 5 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts > index 785889450e8a..f27d5c657f44 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts > +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts > @@ -419,10 +419,6 @@ vreg_l3g_1p2: ldo3 { > }; > }; > > -&dispcc { > - status = "okay"; > -}; > - > &mdss { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 6e9bad8f6f33..0a3a08336b46 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -2684,7 +2684,6 @@ dispcc: clock-controller@af00000 { > #clock-cells = <1>; > #reset-cells = <1>; > #power-domain-cells = <1>; > - status = "disabled"; > }; > > usb_1_hsphy: phy@88e3000 {
On 16.05.2023 17:45, Krzysztof Kozlowski wrote: > Enable Display Subsystem with Visionox VTDR6130 Panel (same as on > MTP8550). > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > > Context in the patch depends on: > 1. https://lore.kernel.org/linux-arm-msm/20230516133011.108093-1-krzysztof.kozlowski@linaro.org/T/#t > 2. https://lore.kernel.org/linux-arm-msm/20230512160452.206585-1-krzysztof.kozlowski@linaro.org/ > > Changes in v2: > 1. dispcc is enabled in DTSI. > 2. Re-order pinctrl and regulators. > 3. Drop mdp. > --- > arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 68 +++++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > index 30b36a149125..ade6ba53ae6b 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts > @@ -431,6 +431,46 @@ &gcc { > <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > }; > > +&mdss { > + status = "okay"; > +}; > + > +&mdss_dsi0 { > + vdda-supply = <&vreg_l3e_1p2>; > + status = "okay"; > + > + panel@0 { > + compatible = "visionox,vtdr6130"; > + reg = <0>; > + > + pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>; > + pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>; > + pinctrl-names = "default", "sleep"; > + > + vci-supply = <&vreg_l13b_3p0>; > + vdd-supply = <&vreg_l11b_1p2>; > + vddio-supply = <&vreg_l12b_1p8>; > + > + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; > + > + port { > + panel0_in: endpoint { > + remote-endpoint = <&mdss_dsi0_out>; > + }; > + }; > + }; > +}; > + > +&mdss_dsi0_out { > + remote-endpoint = <&panel0_in>; > + data-lanes = <0 1 2 3>; > +}; > + > +&mdss_dsi0_phy { > + vdds-supply = <&vreg_l1e_0p88>; > + status = "okay"; > +}; > + > &pcie_1_phy_aux_clk { > status = "disabled"; > }; > @@ -532,6 +572,34 @@ wcd_tx: codec@0,3 { > &tlmm { > gpio-reserved-ranges = <32 8>; > > + sde_dsi_active: sde-dsi-active-state { > + pins = "gpio133"; > + function = "gpio"; > + drive-strength = <8>; > + bias-disable; > + }; > + > + sde_dsi_suspend: sde-dsi-suspend-state { > + pins = "gpio133"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + sde_te_active: sde-te-active-state { > + pins = "gpio86"; > + function = "mdp_vsync"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + sde_te_suspend: sde-te-suspend-state { > + pins = "gpio86"; > + function = "mdp_vsync"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > wcd_default: wcd-reset-n-active-state { > pins = "gpio108"; > function = "gpio";
On Tue, 16 May 2023 17:45:37 +0200, Krzysztof Kozlowski wrote: > Enable the Display Clock Controller by default in SoC DTSI so unused > clocks can be turned off. It does not require any external resources, > so as core SoC component should be always available to boards. > > Applied, thanks! [1/3] arm64: dts: qcom: sm8550: enable DISPCC by default commit: 5ef00c06ea5e4e0de1f63d2c620f671750f73f9b [2/3] arm64: dts: qcom: sm8550-mtp: drop redundant MDP status commit: fbeffa580e30fe7fb748e4ccc39c2b18a137c055 [3/3] arm64: dts: qcom: sm8550-qrd: add display and panel commit: fdb0038e96659f08dae575aae6b4b6b22884d17b Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 785889450e8a..f27d5c657f44 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -419,10 +419,6 @@ vreg_l3g_1p2: ldo3 { }; }; -&dispcc { - status = "okay"; -}; - &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 6e9bad8f6f33..0a3a08336b46 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2684,7 +2684,6 @@ dispcc: clock-controller@af00000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - status = "disabled"; }; usb_1_hsphy: phy@88e3000 {
Enable the Display Clock Controller by default in SoC DTSI so unused clocks can be turned off. It does not require any external resources, so as core SoC component should be always available to boards. Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Changes in v2: 1. New patch --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 - 2 files changed, 5 deletions(-)