| Message ID | 20230511150539.6.Ia0b6ebbaa351e3cd67e201355b9ae67783c7d718@changeid |
|---|---|
| State | New |
| Headers | show |
| Series | [1/6] dt-bindings: interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ broken FW | expand |
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a44aae4ab953..6df9ad8f658f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -463,6 +463,7 @@ gic: interrupt-controller@c000000 { reg = <0 0x0c000000 0 0x40000>, <0 0x0c040000 0 0x200000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gicr-save-quirk; ppi-partitions { ppi_cluster0: interrupt-partition-0 {
Firmware shipped on mt8195 Chromebooks is affected by the GICR save/restore issue as described by the patch ("dt-bindings: interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ broken FW"). Add the quirk property. Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") Signed-off-by: Douglas Anderson <dianders@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 + 1 file changed, 1 insertion(+)