[05/11] tcg/riscv: Use ADD.UW for guest address generation

Message ID	20230503085657.1814850-6-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: dbarboza@ventanamicro.com Subject: [PATCH 05/11] tcg/riscv: Use ADD.UW for guest address generation Date: Wed, 3 May 2023 09:56:51 +0100 Message-Id: <20230503085657.1814850-6-richard.henderson@linaro.org> In-Reply-To: <20230503085657.1814850-1-richard.henderson@linaro.org> References: <20230503085657.1814850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	tcg/riscv: Support for Zba, Zbb, Zicond extensions \| expand [00/11] tcg/riscv: Support for Zba, Zbb, Zicond extensions [01/11] disas/riscv: Decode czero.{eqz,nez} [02/11] tcg/riscv: Probe for Zba, Zbb, Zicond extensions [03/11] tcg/riscv: Support ANDN, ORN, XNOR from Zbb [04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb [05/11] tcg/riscv: Use ADD.UW for guest address generation [06/11] tcg/riscv: Support rotates from Zbb [07/11] tcg/riscv: Support REV8 from Zbb [08/11] tcg/riscv: Support CPOP from Zbb [09/11] tcg/riscv: Improve setcond expansion [10/11] tcg/riscv: Implement movcond [11/11] tcg/riscv: Support CTZ, CLZ from Zbb

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20230503085657.1814850-6-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
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Cc: dbarboza@ventanamicro.com
Subject: [PATCH 05/11] tcg/riscv: Use ADD.UW for guest address generation
Date: Wed,  3 May 2023 09:56:51 +0100
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Series

tcg/riscv: Support for Zba, Zbb, Zicond extensions | expand

Commit Message

Richard Henderson May 3, 2023, 8:56 a.m. UTC

The instruction is a combined zero-extend and add.
Use it for exactly that.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target.c.inc | 33 ++++++++++++++++++++++-----------
 1 file changed, 22 insertions(+), 11 deletions(-)

Comments

Daniel Henrique Barboza May 8, 2023, 12:43 p.m. UTC | #1

On 5/3/23 05:56, Richard Henderson wrote:
> The instruction is a combined zero-extend and add.
> Use it for exactly that.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/riscv/tcg-target.c.inc | 33 ++++++++++++++++++++++-----------
>   1 file changed, 22 insertions(+), 11 deletions(-)
> 
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 53a7f97b29..f64eaa8515 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1039,14 +1039,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
>       tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
>   
>       /* TLB Hit - translate address using addend.  */
> -    addr_adj = addr_reg;
> -    if (TARGET_LONG_BITS == 32) {
> -        addr_adj = TCG_REG_TMP0;
> -        tcg_out_ext32u(s, addr_adj, addr_reg);
> +    if (TARGET_LONG_BITS == 64) {
> +        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
> +    } else if (have_zba) {
> +        tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
> +    } else {
> +        tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
> +        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, TCG_REG_TMP2);
>       }
> -    tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_adj);
>       *pbase = TCG_REG_TMP0;
>   #else
> +    TCGReg base;
> +
>       if (a_mask) {
>           ldst = new_ldst_label(s);
>           ldst->is_ld = is_ld;
> @@ -1061,14 +1065,21 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
>           tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0);
>       }
>   
> -    TCGReg base = addr_reg;
> -    if (TARGET_LONG_BITS == 32) {
> -        tcg_out_ext32u(s, TCG_REG_TMP0, base);
> -        base = TCG_REG_TMP0;
> -    }
>       if (guest_base != 0) {
> -        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
>           base = TCG_REG_TMP0;
> +        if (TARGET_LONG_BITS == 64) {
> +            tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG);
> +        } else if (have_zba) {
> +            tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_REG);
> +        } else {
> +            tcg_out_ext32u(s, base, addr_reg);
> +            tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG);
> +        }
> +    } else if (TARGET_LONG_BITS == 64) {
> +        base = addr_reg;
> +    } else {
> +        base = TCG_REG_TMP0;
> +        tcg_out_ext32u(s, base, addr_reg);

I tried to find a way to remove some of these IFs but all my alternatives weren't
much better.


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>


>       }
>       *pbase = base;
>   #endif

Alistair Francis May 16, 2023, 11:43 p.m. UTC | #2

On Wed, May 3, 2023 at 6:58 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The instruction is a combined zero-extend and add.
> Use it for exactly that.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  tcg/riscv/tcg-target.c.inc | 33 ++++++++++++++++++++++-----------
>  1 file changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 53a7f97b29..f64eaa8515 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1039,14 +1039,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
>      tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
>
>      /* TLB Hit - translate address using addend.  */
> -    addr_adj = addr_reg;
> -    if (TARGET_LONG_BITS == 32) {
> -        addr_adj = TCG_REG_TMP0;
> -        tcg_out_ext32u(s, addr_adj, addr_reg);
> +    if (TARGET_LONG_BITS == 64) {
> +        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
> +    } else if (have_zba) {
> +        tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
> +    } else {
> +        tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
> +        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, TCG_REG_TMP2);
>      }
> -    tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_adj);
>      *pbase = TCG_REG_TMP0;
>  #else
> +    TCGReg base;
> +
>      if (a_mask) {
>          ldst = new_ldst_label(s);
>          ldst->is_ld = is_ld;
> @@ -1061,14 +1065,21 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
>          tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0);
>      }
>
> -    TCGReg base = addr_reg;
> -    if (TARGET_LONG_BITS == 32) {
> -        tcg_out_ext32u(s, TCG_REG_TMP0, base);
> -        base = TCG_REG_TMP0;
> -    }
>      if (guest_base != 0) {
> -        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
>          base = TCG_REG_TMP0;
> +        if (TARGET_LONG_BITS == 64) {
> +            tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG);
> +        } else if (have_zba) {
> +            tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_REG);
> +        } else {
> +            tcg_out_ext32u(s, base, addr_reg);
> +            tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG);
> +        }
> +    } else if (TARGET_LONG_BITS == 64) {
> +        base = addr_reg;
> +    } else {
> +        base = TCG_REG_TMP0;
> +        tcg_out_ext32u(s, base, addr_reg);
>      }
>      *pbase = base;
>  #endif
> --
> 2.34.1
>
>

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 53a7f97b29..f64eaa8515 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1039,14 +1039,18 @@  static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
     tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
 
     /* TLB Hit - translate address using addend.  */
-    addr_adj = addr_reg;
-    if (TARGET_LONG_BITS == 32) {
-        addr_adj = TCG_REG_TMP0;
-        tcg_out_ext32u(s, addr_adj, addr_reg);
+    if (TARGET_LONG_BITS == 64) {
+        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
+    } else if (have_zba) {
+        tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
+    } else {
+        tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
+        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, TCG_REG_TMP2);
     }
-    tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_adj);
     *pbase = TCG_REG_TMP0;
 #else
+    TCGReg base;
+
     if (a_mask) {
         ldst = new_ldst_label(s);
         ldst->is_ld = is_ld;
@@ -1061,14 +1065,21 @@  static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
         tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0);
     }
 
-    TCGReg base = addr_reg;
-    if (TARGET_LONG_BITS == 32) {
-        tcg_out_ext32u(s, TCG_REG_TMP0, base);
-        base = TCG_REG_TMP0;
-    }
     if (guest_base != 0) {
-        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
         base = TCG_REG_TMP0;
+        if (TARGET_LONG_BITS == 64) {
+            tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG);
+        } else if (have_zba) {
+            tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_REG);
+        } else {
+            tcg_out_ext32u(s, base, addr_reg);
+            tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG);
+        }
+    } else if (TARGET_LONG_BITS == 64) {
+        base = addr_reg;
+    } else {
+        base = TCG_REG_TMP0;
+        tcg_out_ext32u(s, base, addr_reg);
     }
     *pbase = base;
 #endif

[05/11] tcg/riscv: Use ADD.UW for guest address generation

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