| Message ID | 20230503085657.1814850-2-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg/riscv: Support for Zba, Zbb, Zicond extensions | expand |
On 5/3/23 05:56, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > disas/riscv.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index d6b0fbe5e8..c0a8b1006a 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -935,6 +935,8 @@ typedef enum { > rv_op_vsetvli = 766, > rv_op_vsetivli = 767, > rv_op_vsetvl = 768, > + rv_op_czero_eqz = 769, > + rv_op_czero_nez = 770, > } rv_op; > > /* structures */ > @@ -2066,7 +2068,9 @@ const rv_opcode_data opcode_data[] = { > { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 }, > { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 }, > { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 }, > - { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 } > + { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }, > + { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > + { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > }; > > /* CSR names */ > @@ -2792,6 +2796,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) > case 45: op = rv_op_minu; break; > case 46: op = rv_op_max; break; > case 47: op = rv_op_maxu; break; > + case 075: op = rv_op_czero_eqz; break; > + case 077: op = rv_op_czero_nez; break; > case 130: op = rv_op_sh1add; break; > case 132: op = rv_op_sh2add; break; > case 134: op = rv_op_sh3add; break;
On Wed, May 3, 2023 at 6:59 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > disas/riscv.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index d6b0fbe5e8..c0a8b1006a 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -935,6 +935,8 @@ typedef enum { > rv_op_vsetvli = 766, > rv_op_vsetivli = 767, > rv_op_vsetvl = 768, > + rv_op_czero_eqz = 769, > + rv_op_czero_nez = 770, > } rv_op; > > /* structures */ > @@ -2066,7 +2068,9 @@ const rv_opcode_data opcode_data[] = { > { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 }, > { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 }, > { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 }, > - { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 } > + { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }, > + { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > + { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > }; > > /* CSR names */ > @@ -2792,6 +2796,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) > case 45: op = rv_op_minu; break; > case 46: op = rv_op_max; break; > case 47: op = rv_op_maxu; break; > + case 075: op = rv_op_czero_eqz; break; > + case 077: op = rv_op_czero_nez; break; > case 130: op = rv_op_sh1add; break; > case 132: op = rv_op_sh2add; break; > case 134: op = rv_op_sh3add; break; > -- > 2.34.1 > >
diff --git a/disas/riscv.c b/disas/riscv.c index d6b0fbe5e8..c0a8b1006a 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -935,6 +935,8 @@ typedef enum { rv_op_vsetvli = 766, rv_op_vsetivli = 767, rv_op_vsetvl = 768, + rv_op_czero_eqz = 769, + rv_op_czero_nez = 770, } rv_op; /* structures */ @@ -2066,7 +2068,9 @@ const rv_opcode_data opcode_data[] = { { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 }, { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 }, { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 }, - { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 } + { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }, + { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, }; /* CSR names */ @@ -2792,6 +2796,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 45: op = rv_op_minu; break; case 46: op = rv_op_max; break; case 47: op = rv_op_maxu; break; + case 075: op = rv_op_czero_eqz; break; + case 077: op = rv_op_czero_nez; break; case 130: op = rv_op_sh1add; break; case 132: op = rv_op_sh2add; break; case 134: op = rv_op_sh3add; break;
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- disas/riscv.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)