diff mbox series

[v4,50/54] tcg/ppc: Remove unused constraints A, B, C, D

Message ID	20230503065729.1745843-51-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: git@xen0n.name, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Daniel Henrique Barboza <danielhb413@gmail.com> Subject: [PATCH v4 50/54] tcg/ppc: Remove unused constraints A, B, C, D Date: Wed, 3 May 2023 07:57:25 +0100 Message-Id: <20230503065729.1745843-51-richard.henderson@linaro.org> In-Reply-To: <20230503065729.1745843-1-richard.henderson@linaro.org> References: <20230503065729.1745843-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	tcg: Simplify calls to load/store helpers \| expand [v4,00/54] tcg: Simplify calls to load/store helpers [v4,01/54] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} [v4,02/54] tcg/i386: Generalize multi-part load overlap test [v4,03/54] tcg/i386: Introduce HostAddress [v4,04/54] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load [v4,05/54] tcg/i386: Introduce tcg_out_testi [v4,06/54] tcg/i386: Introduce prepare_host_addr [v4,07/54] tcg/i386: Use indexed addressing for softmmu fast path [v4,08/54] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st} [v4,09/54] tcg/aarch64: Introduce HostAddress [v4,10/54] tcg/aarch64: Introduce prepare_host_addr [v4,11/54] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} [v4,12/54] tcg/arm: Introduce HostAddress [v4,13/54] tcg/arm: Introduce prepare_host_addr [v4,14/54] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} [v4,15/54] tcg/loongarch64: Introduce HostAddress [v4,16/54] tcg/loongarch64: Introduce prepare_host_addr [v4,17/54] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st} [v4,18/54] tcg/mips: Introduce prepare_host_addr [v4,19/54] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} [v4,20/54] tcg/ppc: Introduce HostAddress [v4,21/54] tcg/ppc: Introduce prepare_host_addr [v4,22/54] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 [v4,23/54] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} [v4,24/54] tcg/riscv: Introduce prepare_host_addr [v4,25/54] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st} [v4,26/54] tcg/s390x: Introduce HostAddress [v4,27/54] tcg/s390x: Introduce prepare_host_addr [v4,28/54] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return [v4,29/54] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} [v4,30/54] tcg: Move TCGLabelQemuLdst to tcg.c [v4,31/54] tcg: Replace REG_P with arg_loc_reg_p [v4,32/54] tcg: Introduce arg_slot_stk_ofs [v4,33/54] tcg: Widen helper_*_st[bw]_mmu val arguments [v4,34/54] tcg: Add routines for calling slow-path helpers [v4,35/54] tcg/i386: Convert tcg_out_qemu_ld_slow_path [v4,36/54] tcg/i386: Convert tcg_out_qemu_st_slow_path [v4,37/54] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path [v4,38/54] tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path [v4,39/54] tcg/loongarch64: Convert tcg_out_qemu_{ld, st}_slow_path [v4,40/54] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path [v4,41/54] tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path [v4,42/54] tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path [v4,43/54] tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path [v4,44/54] tcg/loongarch64: Simplify constraints on qemu_ld/st [v4,45/54] tcg/mips: Remove MO_BSWAP handling [v4,46/54] tcg/mips: Reorg tlb load within prepare_host_addr [v4,47/54] tcg/mips: Simplify constraints on qemu_ld/st [v4,48/54] tcg/ppc: Reorg tcg_out_tlb_read [v4,49/54] tcg/ppc: Adjust constraints on qemu_ld/st [v4,50/54] tcg/ppc: Remove unused constraints A, B, C, D [v4,51/54] tcg/ppc: Remove unused constraint J [v4,52/54] tcg/riscv: Simplify constraints on qemu_ld/st [v4,53/54] tcg/s390x: Use ALGFR in constructing softmmu host address [v4,54/54] tcg/s390x: Simplify constraints on qemu_ld/st

Commit Message

Richard Henderson May 3, 2023, 6:57 a.m. UTC

These constraints have not been used for quite some time.

Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32")
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target-con-str.h | 4 ----
 1 file changed, 4 deletions(-)

diff mbox series

Patch

diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
index f3bf030bc3..9dcbc3df50 100644
--- a/tcg/ppc/tcg-target-con-str.h
+++ b/tcg/ppc/tcg-target-con-str.h
@@ -10,10 +10,6 @@ 
  */
 REGS('r', ALL_GENERAL_REGS)
 REGS('v', ALL_VECTOR_REGS)
-REGS('A', 1u << TCG_REG_R3)
-REGS('B', 1u << TCG_REG_R4)
-REGS('C', 1u << TCG_REG_R5)
-REGS('D', 1u << TCG_REG_R6)
 
 /*
  * Define constraint letters for constants: