diff mbox series

[v2,8/9] drm/msm/dpu: remove struct dpu_hw_pipe_qos_cfg

Message ID 20230502150533.3672840-9-dmitry.baryshkov@linaro.org
State Accepted
Commit a5ebb27bffcc2c1e785abc6782202d9e4041e71c
Headers show
Series drm/msm/dpu: simplify QoS/CDP programming | expand

Commit Message

Dmitry Baryshkov May 2, 2023, 3:05 p.m. UTC
Now as the struct dpu_hw_pipe_qos_cfg consists of only one bool field,
drop the structure and use corresponding bool directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 +++-------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 13 ++-----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 11 +++--------
 3 files changed, 8 insertions(+), 26 deletions(-)

Comments

Jeykumar Sankaran May 5, 2023, 5:21 p.m. UTC | #1
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
> Now as the struct dpu_hw_pipe_qos_cfg consists of only one bool field,
> drop the structure and use corresponding bool directly.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 +++-------
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 13 ++-----------
>   drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 11 +++--------
>   3 files changed, 8 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 341e3a8fc927..2533c4629021 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -568,17 +568,13 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx,
>   }
>   
>   static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
> -		struct dpu_hw_pipe_qos_cfg *cfg)
> +				       bool danger_safe_en)
>   {
> -	u32 qos_ctrl = 0;
> -
>   	if (!ctx)
>   		return;
>   
> -	if (cfg->danger_safe_en)
> -		qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN;
> -
> -	DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL, qos_ctrl);
> +	DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
> +		      danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
>   }
>   
>   static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index aaf6f41d546c..4278c421b6ac 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -163,14 +163,6 @@ struct dpu_sw_pipe_cfg {
>   	struct drm_rect dst_rect;
>   };
>   
> -/**
> - * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration
> - * @danger_safe_en: enable danger safe generation
> - */
> -struct dpu_hw_pipe_qos_cfg {
> -	bool danger_safe_en;
> -};
> -
>   /**
>    * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
>    * @size: size to prefill in bytes, or zero to disable
> @@ -285,11 +277,10 @@ struct dpu_hw_sspp_ops {
>   	/**
>   	 * setup_qos_ctrl - setup QoS control
>   	 * @ctx: Pointer to pipe context
> -	 * @cfg: Pointer to pipe QoS configuration
> -	 *
> +	 * @danger_safe_en: flags controlling enabling of danger/safe QoS/LUT
>   	 */
>   	void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
> -			struct dpu_hw_pipe_qos_cfg *cfg);
> +			       bool danger_safe_en);
>   
>   	/**
>   	 * setup_histogram - setup histograms
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index d1443c4b2915..c8837d0aa0c3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -343,22 +343,17 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
>   	bool enable)
>   {
>   	struct dpu_plane *pdpu = to_dpu_plane(plane);
> -	struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
> -
> -	memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
> -
> -	pipe_qos_cfg.danger_safe_en = enable;
>   
>   	if (!pdpu->is_rt_pipe)
> -		pipe_qos_cfg.danger_safe_en = false;
> +		enable = false;
>   
>   	DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n",
>   		pdpu->pipe - SSPP_VIG0,
> -		pipe_qos_cfg.danger_safe_en,
> +		enable,
>   		pdpu->is_rt_pipe);
>   
>   	pipe->sspp->ops.setup_qos_ctrl(pipe->sspp,
> -			&pipe_qos_cfg);
> +				       enable);
>   }
>   
>   /**
Reviewed-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 341e3a8fc927..2533c4629021 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -568,17 +568,13 @@  static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx,
 }
 
 static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
-		struct dpu_hw_pipe_qos_cfg *cfg)
+				       bool danger_safe_en)
 {
-	u32 qos_ctrl = 0;
-
 	if (!ctx)
 		return;
 
-	if (cfg->danger_safe_en)
-		qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN;
-
-	DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL, qos_ctrl);
+	DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
+		      danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
 }
 
 static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index aaf6f41d546c..4278c421b6ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -163,14 +163,6 @@  struct dpu_sw_pipe_cfg {
 	struct drm_rect dst_rect;
 };
 
-/**
- * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration
- * @danger_safe_en: enable danger safe generation
- */
-struct dpu_hw_pipe_qos_cfg {
-	bool danger_safe_en;
-};
-
 /**
  * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
  * @size: size to prefill in bytes, or zero to disable
@@ -285,11 +277,10 @@  struct dpu_hw_sspp_ops {
 	/**
 	 * setup_qos_ctrl - setup QoS control
 	 * @ctx: Pointer to pipe context
-	 * @cfg: Pointer to pipe QoS configuration
-	 *
+	 * @danger_safe_en: flags controlling enabling of danger/safe QoS/LUT
 	 */
 	void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
-			struct dpu_hw_pipe_qos_cfg *cfg);
+			       bool danger_safe_en);
 
 	/**
 	 * setup_histogram - setup histograms
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index d1443c4b2915..c8837d0aa0c3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -343,22 +343,17 @@  static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
 	bool enable)
 {
 	struct dpu_plane *pdpu = to_dpu_plane(plane);
-	struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
-
-	memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
-
-	pipe_qos_cfg.danger_safe_en = enable;
 
 	if (!pdpu->is_rt_pipe)
-		pipe_qos_cfg.danger_safe_en = false;
+		enable = false;
 
 	DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n",
 		pdpu->pipe - SSPP_VIG0,
-		pipe_qos_cfg.danger_safe_en,
+		enable,
 		pdpu->is_rt_pipe);
 
 	pipe->sspp->ops.setup_qos_ctrl(pipe->sspp,
-			&pipe_qos_cfg);
+				       enable);
 }
 
 /**