| Message ID | 20230430235732.3341119-8-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm/dpu: simplify DPU encoder init | expand |
On 01/05/2023 02:57, Dmitry Baryshkov wrote: > The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the > INTF and WB are statically allocated to each encoder/phys_enc, drop the > atomic_mode_set callback and set the IRQs during encoder init. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Please ignore this for now, I'd like to take another look on my own. I didn't test the CMD panels and they are going to break with this change. > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 -- > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5 ----- > .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 20 +++++-------------- > .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 ++---------- > .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 +--------- > 5 files changed, 8 insertions(+), 43 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index b35e92c658ad..509b4fc7dbc5 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -1106,8 +1106,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, > phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); > > phys->cached_mode = crtc_state->adjusted_mode; > - if (phys->ops.atomic_mode_set) > - phys->ops.atomic_mode_set(phys, crtc_state, conn_state); > } > } > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index 1c096d9390d0..67c4b4e0975d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -68,8 +68,6 @@ struct dpu_encoder_phys; > * @is_master: Whether this phys_enc is the current master > * encoder. Can be switched at enable time. Based > * on split_role and current mode (CMD/VID). > - * @atomic_mode_set: DRM Call. Set a DRM mode. > - * This likely caches the mode, for use at enable. > * @enable: DRM Call. Enable a DRM mode. > * @disable: DRM Call. Disable mode. > * @atomic_check: DRM Call. Atomic check new DRM state. > @@ -97,9 +95,6 @@ struct dpu_encoder_phys_ops { > struct dentry *debugfs_root); > void (*prepare_commit)(struct dpu_encoder_phys *encoder); > bool (*is_master)(struct dpu_encoder_phys *encoder); > - void (*atomic_mode_set)(struct dpu_encoder_phys *encoder, > - struct drm_crtc_state *crtc_state, > - struct drm_connector_state *conn_state); > void (*enable)(struct dpu_encoder_phys *encoder); > void (*disable)(struct dpu_encoder_phys *encoder); > int (*atomic_check)(struct dpu_encoder_phys *encoder, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > index 781290f17714..3ad03465acfe 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > @@ -139,20 +139,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx) > dpu_encoder_underrun_callback(phys_enc->parent, phys_enc); > } > > -static void dpu_encoder_phys_cmd_atomic_mode_set( > - struct dpu_encoder_phys *phys_enc, > - struct drm_crtc_state *crtc_state, > - struct drm_connector_state *conn_state) > -{ > - phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; > - > - phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; > - > - phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; > - > - phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; > -} > - > static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( > struct dpu_encoder_phys *phys_enc) > { > @@ -736,7 +722,6 @@ static void dpu_encoder_phys_cmd_init_ops( > struct dpu_encoder_phys_ops *ops) > { > ops->is_master = dpu_encoder_phys_cmd_is_master; > - ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set; > ops->enable = dpu_encoder_phys_cmd_enable; > ops->disable = dpu_encoder_phys_cmd_disable; > ops->destroy = dpu_encoder_phys_cmd_destroy; > @@ -777,6 +762,11 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( > > dpu_encoder_phys_cmd_init_ops(&phys_enc->ops); > phys_enc->intf_mode = INTF_MODE_CMD; > + phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; > + phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; > + phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; > + phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; > + > cmd_enc->stream_sel = 0; > > atomic_set(&cmd_enc->pending_vblank_cnt, 0); > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index f02ff8f43f47..cf9a0128ff71 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -348,16 +348,6 @@ static bool dpu_encoder_phys_vid_needs_single_flush( > return phys_enc->split_role != ENC_ROLE_SOLO; > } > > -static void dpu_encoder_phys_vid_atomic_mode_set( > - struct dpu_encoder_phys *phys_enc, > - struct drm_crtc_state *crtc_state, > - struct drm_connector_state *conn_state) > -{ > - phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; > - > - phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; > -} > - > static int dpu_encoder_phys_vid_control_vblank_irq( > struct dpu_encoder_phys *phys_enc, > bool enable) > @@ -679,7 +669,6 @@ static int dpu_encoder_phys_vid_get_frame_count( > static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) > { > ops->is_master = dpu_encoder_phys_vid_is_master; > - ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set; > ops->enable = dpu_encoder_phys_vid_enable; > ops->disable = dpu_encoder_phys_vid_disable; > ops->destroy = dpu_encoder_phys_vid_destroy; > @@ -720,6 +709,8 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( > > dpu_encoder_phys_vid_init_ops(&phys_enc->ops); > phys_enc->intf_mode = INTF_MODE_VIDEO; > + phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; > + phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; > > DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx); > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > index b058c69e8778..27479334176b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > @@ -398,15 +398,6 @@ static void dpu_encoder_phys_wb_irq_ctrl( > dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]); > } > > -static void dpu_encoder_phys_wb_atomic_mode_set( > - struct dpu_encoder_phys *phys_enc, > - struct drm_crtc_state *crtc_state, > - struct drm_connector_state *conn_state) > -{ > - > - phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done; > -} > - > static void _dpu_encoder_phys_wb_handle_wbdone_timeout( > struct dpu_encoder_phys *phys_enc) > { > @@ -656,7 +647,6 @@ static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phy > static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops) > { > ops->is_master = dpu_encoder_phys_wb_is_master; > - ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set; > ops->enable = dpu_encoder_phys_wb_enable; > ops->disable = dpu_encoder_phys_wb_disable; > ops->destroy = dpu_encoder_phys_wb_destroy; > @@ -707,6 +697,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_wb_init( > > dpu_encoder_phys_wb_init_ops(&phys_enc->ops); > phys_enc->intf_mode = INTF_MODE_WB_LINE; > + phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done; > > atomic_set(&wb_enc->wbirq_refcount, 0); >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index b35e92c658ad..509b4fc7dbc5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1106,8 +1106,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); phys->cached_mode = crtc_state->adjusted_mode; - if (phys->ops.atomic_mode_set) - phys->ops.atomic_mode_set(phys, crtc_state, conn_state); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 1c096d9390d0..67c4b4e0975d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -68,8 +68,6 @@ struct dpu_encoder_phys; * @is_master: Whether this phys_enc is the current master * encoder. Can be switched at enable time. Based * on split_role and current mode (CMD/VID). - * @atomic_mode_set: DRM Call. Set a DRM mode. - * This likely caches the mode, for use at enable. * @enable: DRM Call. Enable a DRM mode. * @disable: DRM Call. Disable mode. * @atomic_check: DRM Call. Atomic check new DRM state. @@ -97,9 +95,6 @@ struct dpu_encoder_phys_ops { struct dentry *debugfs_root); void (*prepare_commit)(struct dpu_encoder_phys *encoder); bool (*is_master)(struct dpu_encoder_phys *encoder); - void (*atomic_mode_set)(struct dpu_encoder_phys *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state); void (*enable)(struct dpu_encoder_phys *encoder); void (*disable)(struct dpu_encoder_phys *encoder); int (*atomic_check)(struct dpu_encoder_phys *encoder, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 781290f17714..3ad03465acfe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -139,20 +139,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx) dpu_encoder_underrun_callback(phys_enc->parent, phys_enc); } -static void dpu_encoder_phys_cmd_atomic_mode_set( - struct dpu_encoder_phys *phys_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; - - phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; - - phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; - - phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; -} - static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( struct dpu_encoder_phys *phys_enc) { @@ -736,7 +722,6 @@ static void dpu_encoder_phys_cmd_init_ops( struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_cmd_is_master; - ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set; ops->enable = dpu_encoder_phys_cmd_enable; ops->disable = dpu_encoder_phys_cmd_disable; ops->destroy = dpu_encoder_phys_cmd_destroy; @@ -777,6 +762,11 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( dpu_encoder_phys_cmd_init_ops(&phys_enc->ops); phys_enc->intf_mode = INTF_MODE_CMD; + phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; + phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; + phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; + phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; + cmd_enc->stream_sel = 0; atomic_set(&cmd_enc->pending_vblank_cnt, 0); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index f02ff8f43f47..cf9a0128ff71 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -348,16 +348,6 @@ static bool dpu_encoder_phys_vid_needs_single_flush( return phys_enc->split_role != ENC_ROLE_SOLO; } -static void dpu_encoder_phys_vid_atomic_mode_set( - struct dpu_encoder_phys *phys_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; - - phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; -} - static int dpu_encoder_phys_vid_control_vblank_irq( struct dpu_encoder_phys *phys_enc, bool enable) @@ -679,7 +669,6 @@ static int dpu_encoder_phys_vid_get_frame_count( static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_vid_is_master; - ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set; ops->enable = dpu_encoder_phys_vid_enable; ops->disable = dpu_encoder_phys_vid_disable; ops->destroy = dpu_encoder_phys_vid_destroy; @@ -720,6 +709,8 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( dpu_encoder_phys_vid_init_ops(&phys_enc->ops); phys_enc->intf_mode = INTF_MODE_VIDEO; + phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; + phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index b058c69e8778..27479334176b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -398,15 +398,6 @@ static void dpu_encoder_phys_wb_irq_ctrl( dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]); } -static void dpu_encoder_phys_wb_atomic_mode_set( - struct dpu_encoder_phys *phys_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - - phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done; -} - static void _dpu_encoder_phys_wb_handle_wbdone_timeout( struct dpu_encoder_phys *phys_enc) { @@ -656,7 +647,6 @@ static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phy static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_wb_is_master; - ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set; ops->enable = dpu_encoder_phys_wb_enable; ops->disable = dpu_encoder_phys_wb_disable; ops->destroy = dpu_encoder_phys_wb_destroy; @@ -707,6 +697,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_wb_init( dpu_encoder_phys_wb_init_ops(&phys_enc->ops); phys_enc->intf_mode = INTF_MODE_WB_LINE; + phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done; atomic_set(&wb_enc->wbirq_refcount, 0);
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the INTF and WB are statically allocated to each encoder/phys_enc, drop the atomic_mode_set callback and set the IRQs during encoder init. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 -- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5 ----- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 20 +++++-------------- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 ++---------- .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 +--------- 5 files changed, 8 insertions(+), 43 deletions(-)