| Message ID | 20230421223202.115472-1-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Accepted |
| Commit | e2b96ceb554ec964e536dd443217d514684f6c49 |
| Headers | show |
| Series | arm64: dts: s32: add missing cache properties | expand |
On 22/04/2023 00:32, Krzysztof Kozlowski wrote: > As all level 2 and level 3 caches are unified, add required > cache-unified properties to fix warnings like: > > s32g274a-evb.dtb: l2-cache1: 'cache-unified' is a required property > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > > --- > > Please take the patch via sub-arch SoC tree. > --- > arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 ++ > arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > index d8c82da88ca0..5ac1cc9ff50e 100644 > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > @@ -53,11 +53,13 @@ cpu3: cpu@101 { > cluster0_l2: l2-cache0 { > compatible = "cache"; > cache-level = <2>; > + cache-unified; > }; > > cluster1_l2: l2-cache1 { > compatible = "cache"; > cache-level = <2>; > + cache-unified; > }; > }; > > diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi > index 3e306218d533..42409ec56792 100644 > --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi > @@ -62,11 +62,13 @@ cpu3: cpu@101 { > cluster0_l2_cache: l2-cache0 { > compatible = "cache"; > cache-level = <2>; > + cache-unified; > }; > > cluster1_l2_cache: l2-cache1 { > compatible = "cache"; > cache-level = <2>; > + cache-unified; > }; > }; >
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index d8c82da88ca0..5ac1cc9ff50e 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -53,11 +53,13 @@ cpu3: cpu@101 { cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi index 3e306218d533..42409ec56792 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -62,11 +62,13 @@ cpu3: cpu@101 { cluster0_l2_cache: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2_cache: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; };
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: s32g274a-evb.dtb: l2-cache1: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Please take the patch via sub-arch SoC tree. --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 ++ arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 ++ 2 files changed, 4 insertions(+)