| Message ID | 20230423150943.118576-1-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Accepted |
| Commit | 0db4bb045b038ee8c832d4f19013fd88e8d7fd05 |
| Headers | show |
| Series | ARM: dts: broadcom: add missing cache properties | expand |
On 04/23/2023 08:09 AM, Krzysztof Kozlowski wrote: > As all level 2 and level 3 caches are unified, add required > cache-unified properties to fix warnings like: > > bcm963148.dtb: l2-cache0: 'cache-unified' is a required property > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > arch/arm/boot/dts/bcm47622.dtsi | 1 + > arch/arm/boot/dts/bcm63148.dtsi | 1 + > arch/arm/boot/dts/bcm63178.dtsi | 1 + > arch/arm/boot/dts/bcm6756.dtsi | 1 + > arch/arm/boot/dts/bcm6846.dtsi | 1 + > arch/arm/boot/dts/bcm6855.dtsi | 1 + > arch/arm/boot/dts/bcm6878.dtsi | 1 + > 7 files changed, 7 insertions(+) > Reviewed-by: William Zhang <william.zhang@broadcom.com>
On Sun, 23 Apr 2023 17:09:43 +0200, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > As all level 2 and level 3 caches are unified, add required > cache-unified properties to fix warnings like: > > bcm963148.dtb: l2-cache0: 'cache-unified' is a required property > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! -- Florian
diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi index cd25ed2757b7..7cd38de118c3 100644 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -52,6 +52,7 @@ CA7_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi index ba7f265db121..24431de1810e 100644 --- a/arch/arm/boot/dts/bcm63148.dtsi +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -36,6 +36,7 @@ B15_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi index d8268a1e889b..3f9aed96babf 100644 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -44,6 +44,7 @@ CA7_2: cpu@2 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi index 49ecc1f0c18c..1d8d957d65dd 100644 --- a/arch/arm/boot/dts/bcm6756.dtsi +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -52,6 +52,7 @@ CA7_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi index fbc7d3a5dc5f..cf92cf8c4693 100644 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -36,6 +36,7 @@ CA7_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi index 5e0fe26530f1..52d6bc89f9f8 100644 --- a/arch/arm/boot/dts/bcm6855.dtsi +++ b/arch/arm/boot/dts/bcm6855.dtsi @@ -44,6 +44,7 @@ CA7_2: cpu@2 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi index 96529d3d4dc2..2c5d706bac7e 100644 --- a/arch/arm/boot/dts/bcm6878.dtsi +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -36,6 +36,7 @@ CA7_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; };
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: bcm963148.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- arch/arm/boot/dts/bcm47622.dtsi | 1 + arch/arm/boot/dts/bcm63148.dtsi | 1 + arch/arm/boot/dts/bcm63178.dtsi | 1 + arch/arm/boot/dts/bcm6756.dtsi | 1 + arch/arm/boot/dts/bcm6846.dtsi | 1 + arch/arm/boot/dts/bcm6855.dtsi | 1 + arch/arm/boot/dts/bcm6878.dtsi | 1 + 7 files changed, 7 insertions(+)