diff mbox series

arm64: dts: rockchip: add missing cache properties

Message ID 20230421223149.115185-1-krzysztof.kozlowski@linaro.org
State Accepted
Commit 42dcd054a6493e1adf292c3e246d1a2a9258942e
Headers show
Series arm64: dts: rockchip: add missing cache properties | expand

Commit Message

Krzysztof Kozlowski April 21, 2023, 10:31 p.m. UTC 
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

  rk3588s-khadas-edge2.dtb: l3-cache: 'cache-unified' is a dependency of 'cache-size'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

---

Please take the patch via sub-arch SoC tree.
---
 arch/arm64/boot/dts/rockchip/rk3308.dtsi  | 1 +
 arch/arm64/boot/dts/rockchip/rk3328.dtsi  | 1 +
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++
 3 files changed, 11 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index dd228a256a32..2ae4bb7d5e62 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -97,6 +97,7 @@  CPU_SLEEP: cpu-sleep {
 		l2: l2-cache {
 			compatible = "cache";
 			cache-level = <2>;
+			cache-unified;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 6d7a7bf72ac7..e729e7a22b23 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -103,6 +103,7 @@  CPU_SLEEP: cpu-sleep {
 		l2: l2-cache0 {
 			compatible = "cache";
 			cache-level = <2>;
+			cache-unified;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 657c019d27fa..5badc68fe9f0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -230,6 +230,7 @@  l2_cache_l0: l2-cache-l0 {
 			cache-sets = <512>;
 			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
+			cache-unified;
 		};
 
 		l2_cache_l1: l2-cache-l1 {
@@ -239,6 +240,7 @@  l2_cache_l1: l2-cache-l1 {
 			cache-sets = <512>;
 			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
+			cache-unified;
 		};
 
 		l2_cache_l2: l2-cache-l2 {
@@ -248,6 +250,7 @@  l2_cache_l2: l2-cache-l2 {
 			cache-sets = <512>;
 			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
+			cache-unified;
 		};
 
 		l2_cache_l3: l2-cache-l3 {
@@ -257,6 +260,7 @@  l2_cache_l3: l2-cache-l3 {
 			cache-sets = <512>;
 			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
+			cache-unified;
 		};
 
 		l2_cache_b0: l2-cache-b0 {
@@ -266,6 +270,7 @@  l2_cache_b0: l2-cache-b0 {
 			cache-sets = <1024>;
 			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
+			cache-unified;
 		};
 
 		l2_cache_b1: l2-cache-b1 {
@@ -275,6 +280,7 @@  l2_cache_b1: l2-cache-b1 {
 			cache-sets = <1024>;
 			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
+			cache-unified;
 		};
 
 		l2_cache_b2: l2-cache-b2 {
@@ -284,6 +290,7 @@  l2_cache_b2: l2-cache-b2 {
 			cache-sets = <1024>;
 			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
+			cache-unified;
 		};
 
 		l2_cache_b3: l2-cache-b3 {
@@ -293,6 +300,7 @@  l2_cache_b3: l2-cache-b3 {
 			cache-sets = <1024>;
 			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
+			cache-unified;
 		};
 
 		l3_cache: l3-cache {
@@ -301,6 +309,7 @@  l3_cache: l3-cache {
 			cache-line-size = <64>;
 			cache-sets = <4096>;
 			cache-level = <3>;
+			cache-unified;
 		};
 	};