| Message ID | 20230421223155.115339-1-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Accepted |
| Commit | f217d94fc632fece2a41030c2eebc4ed34a48b2a |
| Headers | show |
| Series | arm64: dts: microchip: add missing cache properties | expand |
On 22/04/2023 00:31, Krzysztof Kozlowski wrote: > As all level 2 and level 3 caches are unified, add required > cache-unified and cache-level properties to fix warnings like: > > sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- Anyone from Microchip picking this up? Best regards, Krzysztof
On 17/05/2023 13:38, Steen Hegelund wrote: > Hi Krzysztof, > > I would love to do that, but I am not familiar with the procedure, so maybe you > could help me out? Hm, there is no dedicated maintainer for Microchip ARM64 platforms? I mean one which actually handles the patches? It looks like it, because my recent changes were going through me. This also means that maybe several other changes got ignored. For example: https://lore.kernel.org/all/20230221105039.316819-2-robert.marko@sartura.hr/ https://lore.kernel.org/all/20220420194600.3416282-1-michael@walle.cc/ and others here: https://lore.kernel.org/all/?q=dfn%3Aarch%2Farm64%2Fboot%2Fdts%2Fmicrochip%2F > > This is my understanding of what I need to do: > > Clone the upstream repo listed in MAINTAINERS: > > git clone git@github.com:microchip-ung/linux-upstream.git > cd linux-upstream > git checkout sparx5-next > > Fetch the latest mainline tag from upstream: > > git fetch git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git tag\ > v6.4-rc2 --no-tags > > Rebase the current branch on top of that tag: > > git rebase v6.4-rc2 > > Use b4 to fetch and apply the mail thread patch series: > > b4 shazam -tsl 20230421223155.115339-1-krzysztof.kozlowski@linaro.org You should collect some more patches... For one patch it is probably too much effort. I can take it instead. > > Tag the current work for inclusion in the next kernel version with a decription: > > git tag -s sparx5-dt-6.5 git tag -a -s sparx5-dt-6.5 Because you need to provide some explanation. Take a look at examples from other sub-arch maintainers what to write in the tag: https://lore.kernel.org/soc/20230410170233.5931-1-andersson@kernel.org/T/#u https://lore.kernel.org/soc/20230405080438.156805-1-krzysztof.kozlowski@linaro.org/T/ > > Push work that to the public repo: > > git push origin sparx5-dt-6.5 > > Create a pull request (to stdout) to be included in an email to the maintainers: > > git request-pull v6.4-rc2 origin sparx5-dt-6.5 > > Send this PR to the maintainers and CC co-maintainers. > > Is this the correct procedure? > Who should I send the PR email to (is there a list somewhere)? Yes, it's correct with few nits I mentioned. You send it to arm@, soc@, Olof and Arnd. Addresses are in examples above. I will be preparing today the pull with various cleanups for arm-soc, so I will take the patch if you do not mind. For future (and all previous patches), please think what do you (you=Microchip) want to do with it. If you do not handle the patches, then someone should or the platform should be marked as "Odd fixes". Best regards, Krzysztof
On Sat, 22 Apr 2023 00:31:55 +0200, Krzysztof Kozlowski wrote: > As all level 2 and level 3 caches are unified, add required > cache-unified and cache-level properties to fix warnings like: > > sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property > > Applied, thanks! [1/1] arm64: dts: microchip: add missing cache properties https://git.kernel.org/krzk/linux-dt/c/f217d94fc632fece2a41030c2eebc4ed34a48b2a Best regards,
Hey, On Wed, May 17, 2023 at 02:10:53PM +0200, Krzysztof Kozlowski wrote: > On 17/05/2023 13:38, Steen Hegelund wrote: > > Hi Krzysztof, > > > > I would love to do that, but I am not familiar with the procedure, so maybe you > > could help me out? > > Hm, there is no dedicated maintainer for Microchip ARM64 platforms? I > mean one which actually handles the patches? > > It looks like it, because my recent changes were going through me. This > also means that maybe several other changes got ignored. For example: Aye and the branches etc in the repo itself are all a wee bit stale. > > This is my understanding of what I need to do: > > > > Clone the upstream repo listed in MAINTAINERS: > > > > git clone git@github.com:microchip-ung/linux-upstream.git > > cd linux-upstream > > git checkout sparx5-next > > > > Fetch the latest mainline tag from upstream: > > > > git fetch git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git tag\ > > v6.4-rc2 --no-tags > > > > Rebase the current branch on top of that tag: > > > > git rebase v6.4-rc2 > > > > Use b4 to fetch and apply the mail thread patch series: > > > > b4 shazam -tsl 20230421223155.115339-1-krzysztof.kozlowski@linaro.org > > You should collect some more patches... For one patch it is probably too > much effort. I can take it instead. > > > Tag the current work for inclusion in the next kernel version with a decription: > > > > git tag -s sparx5-dt-6.5 > > git tag -a -s sparx5-dt-6.5 > > Because you need to provide some explanation. Take a look at examples > from other sub-arch maintainers what to write in the tag: > > https://lore.kernel.org/soc/20230410170233.5931-1-andersson@kernel.org/T/#u > > https://lore.kernel.org/soc/20230405080438.156805-1-krzysztof.kozlowski@linaro.org/T/ > > > > > Push work that to the public repo: > > > > git push origin sparx5-dt-6.5 > > > > Create a pull request (to stdout) to be included in an email to the maintainers: > > > > git request-pull v6.4-rc2 origin sparx5-dt-6.5 > > > > Send this PR to the maintainers and CC co-maintainers. > > > > Is this the correct procedure? > > Who should I send the PR email to (is there a list somewhere)? > > Yes, it's correct with few nits I mentioned. > > You send it to arm@, soc@, Olof and Arnd. Addresses are in examples above. > > I will be preparing today the pull with various cleanups for arm-soc, so > I will take the patch if you do not mind. > > For future (and all previous patches), please think what do you > (you=Microchip) want to do with it. If you do not handle the patches, > then someone should or the platform should be marked as "Odd fixes". If noone is set up to actually be the maintainer of the tree, and the patch volume is low, it might be a good idea to combine its maintenance with some of the other microchip trees. I've added Nicolas to CC here, since he is the main maintainer for the 32-bit ARM Microchip stuff. For some context, I maintain the RISC-V Microchip bits and a few other things like dt-bindings and some non-microchip RISC-V platforms. If you like, I could easily pick up patches for arch/arm64/boot/dts/microchip/* as I am already sending PRs to Arnd for other trees and another branch would not be much overhead! Clearly I do not know the hardware at all, and reviewing the patches would still be up to you, but I could handle the "administrative" side of things (applying the patches & sending PRs) if that would be helpful? Otherwise, Nicolas & I could probably help you through setting things up to send PRs without taking up Krzysztof's time? Either works for me! Thanks, Conor.
On 17/05/2023 at 14:58, Conor Dooley wrote: > On Wed, May 17, 2023 at 02:46:38PM +0200, Steen Hegelund wrote: >> On Wed, 2023-05-17 at 13:37 +0100, Conor Dooley wrote: >>> On Wed, May 17, 2023 at 02:10:53PM +0200, Krzysztof Kozlowski wrote: > >>>> For future (and all previous patches), please think what do you >>>> (you=Microchip) want to do with it. If you do not handle the patches, >>>> then someone should or the platform should be marked as "Odd fixes". >>> >>> If noone is set up to actually be the maintainer of the tree, and the >>> patch volume is low, it might be a good idea to combine its maintenance >>> with some of the other microchip trees. >>> >>> I've added Nicolas to CC here, since he is the main maintainer for the >>> 32-bit ARM Microchip stuff. For some context, I maintain the RISC-V >>> Microchip bits and a few other things like dt-bindings and some >>> non-microchip RISC-V platforms. >>> >>> If you like, I could easily pick up patches for >>> arch/arm64/boot/dts/microchip/* as I am already sending PRs to Arnd for >>> other trees and another branch would not be much overhead! >>> >>> Clearly I do not know the hardware at all, and reviewing the patches >>> would still be up to you, but I could handle the "administrative" side >>> of things (applying the patches & sending PRs) if that would be helpful? >>> >>> Otherwise, Nicolas & I could probably help you through setting things up >>> to send PRs without taking up Krzysztof's time? >>> >>> Either works for me! >> >> It would be preferable for me if you (Conor) would handle the >> arch/arm64/boot/dts/microchip/* tree as you suggested. It is not often we >> update it, so it will hopefully be low overhead for you. > > Okay. I will send a patch for MAINTAINERS then - although I'll give > Nicolas a change to look at it this thread first ;) Yes, sure thing that I can be added as maintainer of the arm64 part of Microchip, you can add me to a MAINTAINERS entry taking care of this and use our group git tree for this purpose, we'll add branches for that. > If the mpu32 guys ever decide to become mpu64 then we can perhaps > re-visit things. > >> Thanks to both of you for the assistance. > > No worries chief. Thanks Conor for the heads-up. Best regards, Nicolas
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 0367a00a269b..6f7651b06478 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -52,6 +52,8 @@ cpu1: cpu@1 { }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; };
As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Please take the patch via sub-arch SoC tree. --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 ++ 1 file changed, 2 insertions(+)