| Message ID | 20230421223159.115412-1-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Accepted |
| Commit | ae1c0d6eb45a7839396337ea597090542b294c7d |
| Headers | show |
| Series | arm64: dts: marvell: add missing cache properties | expand |
On 22/04/2023 00:31, Krzysztof Kozlowski wrote: > As all level 2 and level 3 caches are unified, add required > cache-unified properties to fix warnings like: > > ac5-98dx35xx-rd.dtb: l2-cache: 'cache-unified' is a required property > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Please take the patch via sub-arch SoC tree. Hi Andrew and Gregory, Could you grab this one? Best regards, Krzysztof
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> writes: > On 22/04/2023 00:31, Krzysztof Kozlowski wrote: >> As all level 2 and level 3 caches are unified, add required >> cache-unified properties to fix warnings like: >> >> ac5-98dx35xx-rd.dtb: l2-cache: 'cache-unified' is a required property >> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> >> --- >> >> Please take the patch via sub-arch SoC tree. > > Hi Andrew and Gregory, > > Could you grab this one? Applied on mvebu/dt64 Thanks, Gregory > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 8bce64069138..c9ce1010c415 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -50,6 +50,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index 990f70303fe6..3ed6fba1f438 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -52,6 +52,7 @@ l2: l2-cache { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index a7b8e001cc9c..cf6a96ddcf40 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -82,6 +82,7 @@ l2_0: l2-cache0 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; l2_1: l2-cache1 { @@ -90,6 +91,7 @@ l2_1: l2-cache1 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi index 7740098fd108..8848238f9565 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi @@ -82,6 +82,7 @@ l2_0: l2-cache0 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; l2_1: l2-cache1 { @@ -90,6 +91,7 @@ l2_1: l2-cache1 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; }; };
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: ac5-98dx35xx-rd.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Please take the patch via sub-arch SoC tree. --- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++ arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++ 4 files changed, 6 insertions(+)