diff mbox series

arm64: dts: lg: add missing cache properties

Message ID 20230421223201.115439-1-krzysztof.kozlowski@linaro.org
State Accepted
Commit 1193001081e98d13c786fe0cae407cb747104cdc
Headers show
Series arm64: dts: lg: add missing cache properties | expand

Commit Message

Krzysztof Kozlowski April 21, 2023, 10:32 p.m. UTC
As all level 2 and level 3 caches are unified, add required
cache-unified and cache-level properties to fix warnings like:

  lg1312-ref.dtb: l2-cache0: 'cache-level' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

---

Please take the patch via sub-arch SoC tree.
---
 arch/arm64/boot/dts/lg/lg1312.dtsi | 2 ++
 arch/arm64/boot/dts/lg/lg1313.dtsi | 2 ++
 2 files changed, 4 insertions(+)

Comments

Krzysztof Kozlowski May 16, 2023, 4:31 p.m. UTC | #1
On 22/04/2023 00:32, Krzysztof Kozlowski wrote:
> As all level 2 and level 3 caches are unified, add required
> cache-unified and cache-level properties to fix warnings like:
> 
>   lg1312-ref.dtb: l2-cache0: 'cache-level' is a required property
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> ---
> 
> Please take the patch via sub-arch SoC tree.

Ping?

Best regards,
Krzysztof
Krzysztof Kozlowski July 13, 2023, 6:53 a.m. UTC | #2
On Sat, 22 Apr 2023 00:32:01 +0200, Krzysztof Kozlowski wrote:
> As all level 2 and level 3 caches are unified, add required
> cache-unified and cache-level properties to fix warnings like:
> 
>   lg1312-ref.dtb: l2-cache0: 'cache-level' is a required property
> 
> 

This was waiting on the list for long time, so I am picking it up. If someone
else prefers to take it, let me know.

Applied, thanks!

[1/1] arm64: dts: lg: add missing cache properties
      https://git.kernel.org/krzk/linux-dt/c/1193001081e98d13c786fe0cae407cb747104cdc

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 78ae73d0cf36..48ec4ebec0a8 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -48,6 +48,8 @@  cpu3: cpu@3 {
 		};
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index 2173316573be..3869460aa5dc 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -48,6 +48,8 @@  cpu3: cpu@3 {
 		};
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
 		};
 	};