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[1/2] ARM: head: Tidy up CPU mode setting on kernel entry

Message ID 1328901508-22076-1-git-send-email-dave.martin@linaro.org
State Not Applicable
Headers show

Commit Message

Dave Martin Feb. 10, 2012, 7:18 p.m. UTC 
This patch does two things:

  * Ensure that asynchronous aborts are masked at kernel entry.
    The bootloader should be masking these anyway, but this reduces
    the damage window just in case it doesn't.

  * Enter svc mode via exception return to ensure that CPU state is
    properly serialised.  This does not matter when switching from
    an ordinary privileged mode ("PL1" modes in ARMv7-AR rev C
    parlance), but it potentially does matter when switching from a
    another privileged mode such as hyp mode.

This should allow the kernel to boot safely either from svc mode or
hyp mode, even if no support for use of the ARM Virtualization
Extensions is built into the kernel.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/kernel/head.S |   23 ++++++++++++++++++++---
 1 files changed, 20 insertions(+), 3 deletions(-)

Comments

Nicolas Pitre Feb. 13, 2012, 2:13 a.m. UTC | #1 
On Fri, 10 Feb 2012, Dave Martin wrote:

> @@ -91,8 +106,9 @@ ENTRY(stext)
>   THUMB(	.thumb			)	@ switch to Thumb now.
>   THUMB(1:			)
>  
> -	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
> -						@ and irqs disabled
> +	@ ensure svc mode and all interrupts masked
> +	safe_svcmode_maskall r4

Why not using r9 for the temporary reg as the original?

> @@ -346,7 +362,8 @@ ENTRY(secondary_startup)
>  	 * the processor type - there is no need to check the machine type
>  	 * as it has already been validated by the primary processor.
>  	 */
> -	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
> +	safe_svcmode_maskall r4

Ditto here.


Nicolas
diff mbox

Patch

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 6d57911..0ccf042 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -64,6 +64,21 @@ 
 #endif
 
 /*
+ * Helper macro to enter SVC mode cleanly and mask interrupts.  reg is a
+ * scratch register available for the macro to overwrite.
+ */
+.macro safe_svcmode_maskall reg:req
+	mrs	\reg , cpsr
+	orr	\reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT
+	bic	\reg , \reg , #MODE_MASK
+	orr	\reg , \reg , #SVC_MODE
+	msr	spsr_cxsf, \reg
+	adr	\reg , BSYM(1f)
+	movs	pc, \reg
+1:
+.endm
+
+/*
  * Kernel startup entry point.
  * ---------------------------
  *
@@ -91,8 +106,9 @@  ENTRY(stext)
  THUMB(	.thumb			)	@ switch to Thumb now.
  THUMB(1:			)
 
-	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
-						@ and irqs disabled
+	@ ensure svc mode and all interrupts masked
+	safe_svcmode_maskall r4
+
 	mrc	p15, 0, r9, c0, c0		@ get processor id
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
@@ -346,7 +362,8 @@  ENTRY(secondary_startup)
 	 * the processor type - there is no need to check the machine type
 	 * as it has already been validated by the primary processor.
 	 */
-	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
+	safe_svcmode_maskall r4
+
 	mrc	p15, 0, r9, c0, c0		@ get processor id
 	bl	__lookup_processor_type
 	movs	r10, r5				@ invalid processor?