diff mbox series

[v1,2/2] arm64: dts: imx8mp: Add ISI DT node

Message ID 20230417055627.16482-3-laurent.pinchart@ideasonboard.com
State Superseded
Headers show
Series arm64: dts: imx8mp: Enable CSIS and ISI in DT | expand

Commit Message

Laurent Pinchart April 17, 2023, 5:56 a.m. UTC
Add a DT node for the i.MX8MP ISI instance, and model to connection to
two CSI-2 receivers (CSIS).

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)

Comments

Alexander Stein April 17, 2023, 6:13 a.m. UTC | #1
Hi Laurent,

thanks for those ISI patches.

Am Montag, 17. April 2023, 07:56:27 CEST schrieb Laurent Pinchart:
> Add a DT node for the i.MX8MP ISI instance, and model to connection to
> two CSI-2 receivers (CSIS).
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 2a374a4c14a2..cc7a938b6f73 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1239,6 +1239,38 @@ ldb_lvds_ch1: endpoint {
>  				};
>  			};
> 
> +			isi_0: isi@32e00000 {
> +				compatible = "fsl,imx8mp-isi";
> +				reg = <0x32e00000 0x4000>;
> +				interrupts = <GIC_SPI 16 
IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 42 
IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk 
IMX8MP_CLK_MEDIA_AXI_ROOT>,
> +					 <&clk 
IMX8MP_CLK_MEDIA_APB_ROOT>;
> +				clock-names = "axi", "apb";
> +				fsl,blk-ctrl = <&media_blk_ctrl>;
> +				power-domains = <&media_blk_ctrl 
IMX8MP_MEDIABLK_PD_ISI>;
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +						isi_in_0: endpoint 
{

I'm not sure if DT graph is different, but usually there is an empty line 
between properties and subnodes.

Best regards,
Alexander

> +							remote-
endpoint = <&mipi_csi_0_out>;
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +						isi_in_1: endpoint 
{
> +							remote-
endpoint = <&mipi_csi_1_out>;
> +						};
> +					};
> +				};
> +			};
> +
>  			mipi_csi_0: csi@32e40000 {
>  				compatible = "fsl,imx8mp-mipi-csi2", 
"fsl,imx8mm-mipi-csi2";
>  				reg = <0x32e40000 0x10000>;
> @@ -1265,6 +1297,9 @@ port@0 {
> 
>  					port@1 {
>  						reg = <1>;
> +						mipi_csi_0_out: 
endpoint {
> +							remote-
endpoint = <&isi_in_0>;
> +						};
>  					};
>  				};
>  			};
> @@ -1295,6 +1330,9 @@ port@0 {
> 
>  					port@1 {
>  						reg = <1>;
> +						mipi_csi_1_out: 
endpoint {
> +							remote-
endpoint = <&isi_in_1>;
> +						};
>  					};
>  				};
>  			};
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 2a374a4c14a2..cc7a938b6f73 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1239,6 +1239,38 @@  ldb_lvds_ch1: endpoint {
 				};
 			};
 
+			isi_0: isi@32e00000 {
+				compatible = "fsl,imx8mp-isi";
+				reg = <0x32e00000 0x4000>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+				clock-names = "axi", "apb";
+				fsl,blk-ctrl = <&media_blk_ctrl>;
+				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						isi_in_0: endpoint {
+							remote-endpoint = <&mipi_csi_0_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						isi_in_1: endpoint {
+							remote-endpoint = <&mipi_csi_1_out>;
+						};
+					};
+				};
+			};
+
 			mipi_csi_0: csi@32e40000 {
 				compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
 				reg = <0x32e40000 0x10000>;
@@ -1265,6 +1297,9 @@  port@0 {
 
 					port@1 {
 						reg = <1>;
+						mipi_csi_0_out: endpoint {
+							remote-endpoint = <&isi_in_0>;
+						};
 					};
 				};
 			};
@@ -1295,6 +1330,9 @@  port@0 {
 
 					port@1 {
 						reg = <1>;
+						mipi_csi_1_out: endpoint {
+							remote-endpoint = <&isi_in_1>;
+						};
 					};
 				};
 			};