| Message ID | 20230413155043.102307-1-Frank.Li@nxp.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/1] arm64: dts: imx8: fix USB 3.0 Gadget Failure in QM & QXPB0 at super speed | expand |
> > Caution: EXT Email > > Resolve USB 3.0 gadget failure for QM and QXPB0 in super speed mode with > single > IN and OUT endpoints, like mass storage devices, due to incorrect > ACTUAL_MEM_SIZE in ep_cap2 (32k instead of actual 18k). Implement dt > property > cdns,on-chip-buff-size to override ep_cap2 and set it to 18k for imx8QM and > imx8QXP chips. No adverse effects for 8QXP C0. > > Fixes: dce49449e04ff ("usb: cdns3: allocate TX FIFO size according to > composite EP number") > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- Shawn: Ping, it is important fixes for 8qm. > arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > index b32c2e199c160..030c273c8be40 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > @@ -171,6 +171,7 @@ usbotg3_cdns3: usb@5b120000 { > interrupt-names = "host", "peripheral", "otg", "wakeup"; > phys = <&usb3_phy>; > phy-names = "cdns3,usb3-phy"; > + cdns,on-chip-buff-size = /bits/ 16 <18>; > status = "disabled"; > }; > }; > -- > 2.34.1
> > > --- > > arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > > index b32c2e199c160..030c273c8be40 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > > @@ -171,6 +171,7 @@ usbotg3_cdns3: usb@5b120000 { > > interrupt-names = "host", "peripheral", "otg", "wakeup"; > > phys = <&usb3_phy>; > > phy-names = "cdns3,usb3-phy"; > > + cdns,on-chip-buff-size = /bits/ 16 <18>; > > The property is defined as uint32 in the bindings. Not sure why we > need to enforce 16-bits here. Driver code use 16bit, if use 32bit here, it will be zero. I have not checked bindings doc. Next version will fix binding doc. Frank > > Shawn > > > status = "disabled"; > > }; > > }; > > -- > > 2.34.1 > >
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index b32c2e199c160..030c273c8be40 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -171,6 +171,7 @@ usbotg3_cdns3: usb@5b120000 { interrupt-names = "host", "peripheral", "otg", "wakeup"; phys = <&usb3_phy>; phy-names = "cdns3,usb3-phy"; + cdns,on-chip-buff-size = /bits/ 16 <18>; status = "disabled"; }; };
Resolve USB 3.0 gadget failure for QM and QXPB0 in super speed mode with single IN and OUT endpoints, like mass storage devices, due to incorrect ACTUAL_MEM_SIZE in ep_cap2 (32k instead of actual 18k). Implement dt property cdns,on-chip-buff-size to override ep_cap2 and set it to 18k for imx8QM and imx8QXP chips. No adverse effects for 8QXP C0. Fixes: dce49449e04ff ("usb: cdns3: allocate TX FIFO size according to composite EP number") Signed-off-by: Frank Li <Frank.Li@nxp.com> --- arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 1 + 1 file changed, 1 insertion(+)