| Message ID | 20230412164920.21862-3-quic_kathirav@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | None | expand |
On 12.04.2023 18:49, Kathiravan T wrote: > Add the definition for the UART1 found on IPQ5332 SoC. > > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index 12e0e179e139..c32217530b41 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -218,6 +218,16 @@ > status = "disabled"; > }; > > + blsp1_uart1: serial@78b0000 { > + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > + reg = <0x078b0000 0x200>; > + interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, > + <&gcc GCC_BLSP1_AHB_CLK>; > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + > blsp1_spi0: spi@78b5000 { > compatible = "qcom,spi-qup-v2.2.1"; > reg = <0x078b5000 0x600>;
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 12e0e179e139..c32217530b41 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -218,6 +218,16 @@ status = "disabled"; }; + blsp1_uart1: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + blsp1_spi0: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b5000 0x600>;
Add the definition for the UART1 found on IPQ5332 SoC. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)