diff mbox series

[PULL,2/2] target/arm: Copy guarded bit in combine_cacheattrs

Message ID 20230410141408.3564269-3-peter.maydell@linaro.org
State Accepted
Commit 8539dc00552e8ea60420856fc1262c8299bc6308
Headers show
Series [PULL,1/2] target/arm: PTE bit GP only applies to stage1 | expand

Commit Message

Peter Maydell April 10, 2023, 2:14 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>

The guarded bit comes from the stage1 walk.

Fixes: Coverity CID 1507929
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 58a6de09bc9..6d72950a795 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2576,6 +2576,7 @@  static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
 
     assert(!s1.is_s2_format);
     ret.is_s2_format = false;
+    ret.guarded = s1.guarded;
 
     if (s1.attrs == 0xf0) {
         tagged = true;