@@ -70,6 +70,10 @@ properties:
power-domains:
maxItems: 1
+ qcom,ice:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the Inline Crypto Engine node
+
reg:
minItems: 1
maxItems: 2
@@ -187,6 +191,28 @@ allOf:
# TODO: define clock bindings for qcom,msm8994-ufshc
+ - if:
+ properties:
+ qcom,ice:
+ minItems: 1
+ maxItems: 1
+ then:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 1
+ clocks:
+ minItems: 8
+ maxItems: 8
+ else:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+ clocks:
+ minItems: 9
+ maxItems: 11
+
unevaluatedProperties: false
examples:
Starting with SM8550, the ICE will have its own devicetree node so add the qcom,ice property to reference it. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- The v5 is here: https://lore.kernel.org/all/20230403200530.2103099-3-abel.vesa@linaro.org/ Changes since v5: * dropped the sm8550 specific subschema and replaced it with one that mutually excludes the qcom,ice vs both the ICE specific reg range and the ICE clock Changes since v4: * Added check for sm8550 compatible w.r.t. qcom,ice in order to enforce it while making sure none of the other platforms are allowed to use it Changes since v3: * dropped the "and drop core clock" part from subject line Changes since v2: * dropped all changes except the qcom,ice property .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+)