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[v2,1/2] dt-bindings: i2c: cadence: Document `resets` property

Message ID 20230406154834.171577-1-lars@metafoo.de
State New
Headers show
Series [v2,1/2] dt-bindings: i2c: cadence: Document `resets` property | expand

Commit Message

Lars-Peter Clausen April 6, 2023, 3:48 p.m. UTC
The Cadence I2C controller has an external reset that needs to be
de-asserted before the I2C controller can be accessed.

Document the `resets` devicetree property that can be used to describe how
the reset signal is connected.

While the reset signal will always be present in hardware the devicetree
property is kept optional for backwards compatibility with existing systems
that do not specify the reset property and where the reset signal might not
be controlled by operating system.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes since v1:
	* Add `resets` property to example
---
 Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Michal Simek April 13, 2023, 10:20 a.m. UTC | #1
On 4/6/23 17:48, Lars-Peter Clausen wrote:
> The Cadence I2C controller has an external reset that needs to be
> de-asserted before the I2C controller can be accessed.
> 
> Document the `resets` devicetree property that can be used to describe how
> the reset signal is connected.
> 
> While the reset signal will always be present in hardware the devicetree
> property is kept optional for backwards compatibility with existing systems
> that do not specify the reset property and where the reset signal might not
> be controlled by operating system.
> 
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> Changes since v1:
> 	* Add `resets` property to example
> ---
>   Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
> index 9187015d9702..cb24d7b3221c 100644
> --- a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
> +++ b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
> @@ -24,6 +24,9 @@ properties:
>     clocks:
>       minItems: 1
>   
> +  resets:
> +    maxItems: 1
> +
>     interrupts:
>       maxItems: 1
>   
> @@ -59,6 +62,7 @@ examples:
>       i2c@e0004000 {
>           compatible = "cdns,i2c-r1p10";
>           clocks = <&clkc 38>;
> +        resets = <&rstc 288>;
>           interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>           reg = <0xe0004000 0x1000>;
>           clock-frequency = <400000>;

Acked-by: Michal Simek <michal.simek@amd.com>

Thanks,
Michal
Wolfram Sang April 13, 2023, 4:44 p.m. UTC | #2
On Thu, Apr 06, 2023 at 08:48:33AM -0700, Lars-Peter Clausen wrote:
> The Cadence I2C controller has an external reset that needs to be
> de-asserted before the I2C controller can be accessed.
> 
> Document the `resets` devicetree property that can be used to describe how
> the reset signal is connected.
> 
> While the reset signal will always be present in hardware the devicetree
> property is kept optional for backwards compatibility with existing systems
> that do not specify the reset property and where the reset signal might not
> be controlled by operating system.
> 
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Applied to for-next, thanks!
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
index 9187015d9702..cb24d7b3221c 100644
--- a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
+++ b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
@@ -24,6 +24,9 @@  properties:
   clocks:
     minItems: 1
 
+  resets:
+    maxItems: 1
+
   interrupts:
     maxItems: 1
 
@@ -59,6 +62,7 @@  examples:
     i2c@e0004000 {
         compatible = "cdns,i2c-r1p10";
         clocks = <&clkc 38>;
+        resets = <&rstc 288>;
         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
         reg = <0xe0004000 0x1000>;
         clock-frequency = <400000>;