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[2/2] target/arm: Copy guarded bit in combine_cacheattrs

Message ID 20230407185149.3253946-3-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: BTI guarded bit fixes | expand

Commit Message

Richard Henderson April 7, 2023, 6:51 p.m. UTC 
The guarded bit comes from the stage1 walk.

Fixes: Coverity CID 1507929
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/ptw.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 58a6de09bc..6d72950a79 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2576,6 +2576,7 @@  static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
 
     assert(!s1.is_s2_format);
     ret.is_s2_format = false;
+    ret.guarded = s1.guarded;
 
     if (s1.attrs == 0xf0) {
         tagged = true;