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[v2,1/2] dt-bindings: mmc: arasan,sdci: Add Xilinx Versal Net compatible

Message ID 20230330065240.3532010-2-sai.krishna.potthuri@amd.com
State Accepted
Commit 8aa7206411fce5a2c6e2643df5c91e6d3e583ba8
Headers show
Series mmc: sdhci-of-arasan: Add eMMC5.1 support for Xilinx Versal Net | expand

Commit Message

Sai Krishna Potthuri March 30, 2023, 6:52 a.m. UTC 
Add Xilinx Versal Net compatible to support eMMC 5.1 PHY.

Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
---
 Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 5 +++++
 1 file changed, 5 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
index 8296c34cfa00..9166ac061b44 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
@@ -27,6 +27,7 @@  allOf:
             enum:
               - xlnx,zynqmp-8.9a
               - xlnx,versal-8.9a
+              - xlnx,versal-net-emmc
     then:
       properties:
         clock-output-names:
@@ -62,6 +63,10 @@  properties:
         description:
           For this device it is strongly suggested to include
           clock-output-names and '#clock-cells'.
+      - const: xlnx,versal-net-emmc     # Versal Net eMMC PHY
+        description:
+          For this device it is strongly suggested to include
+          clock-output-names and '#clock-cells'.
       - items:
           - const: intel,lgm-sdhci-5.1-emmc     # Intel LGM eMMC PHY
           - const: arasan,sdhci-5.1