| Message ID | 20230327083647.22017-11-angelogioacchino.delregno@collabora.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | MT6795 Helio X10 and Sony Xperia M5: DT step 2! | expand |
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index b721971d4e5e..a8b2c4517e79 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -647,5 +647,17 @@ mmsys: syscon@14000000 { <&gce 1 CMDQ_THR_PRIO_HIGHEST>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6795-vdecsys"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@18000000 { + compatible = "mediatek,mt6795-vencsys"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; + }; }; };
In prepration for adding the IOMMUs and LARBs of this SoC, add the VDECSYS and VENCSYS clock controller nodes, providing clocks for the vcodec stateful decoder and stateful decoder hardware. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)