| Message ID | 20230321011821.635977-12-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [RFC,v2,01/13] drm/atomic-helper: split not-scaling part of drm_atomic_helper_check_plane_state | expand |
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote: > We need to know if the platform supports inline rotation on any of the > SSPP blocks or not. Add this information to struct dpu_caps in a form of > the boolean field has_inline_rot. > So even for this one, will a helper to detect it from the list of sspps be better? We are now duplicating information from sspp to dpu caps for convenience and nothing wrong with it if the helper will get called like every atomic check . But looking at the next patch, it seems we use this information only once during dpu_plane_init(), so why not add a helper to find this out? > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 2d6944a9679a..33527ec7c938 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -489,6 +489,7 @@ static const struct dpu_caps sc7280_dpu_caps = { > .ubwc_version = DPU_HW_UBWC_VER_30, > .has_dim_layer = true, > .has_idle_pc = true, > + .has_inline_rot = true, > .max_linewidth = 2400, > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > .format_list = plane_formats_yuv, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 4847aae78db2..cc64fb2e815f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -400,6 +400,7 @@ struct dpu_rotation_cfg { > * @has_dim_layer dim layer feature status > * @has_idle_pc indicate if idle power collapse feature is supported > * @has_3d_merge indicate if 3D merge is supported > + * @has_inline_rot indicate if inline rotation is supported > * @max_linewidth max linewidth for sspp > * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes > * @max_hdeci_exp max horizontal decimation supported (max is 2^value) > @@ -416,6 +417,7 @@ struct dpu_caps { > bool has_dim_layer; > bool has_idle_pc; > bool has_3d_merge; > + bool has_inline_rot; > /* SSPP limits */ > u32 max_linewidth; > u32 pixel_ram_size;
On Thu, 25 May 2023 at 02:20, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote: > > > > On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote: > > We need to know if the platform supports inline rotation on any of the > > SSPP blocks or not. Add this information to struct dpu_caps in a form of > > the boolean field has_inline_rot. > > > > So even for this one, will a helper to detect it from the list of sspps > be better? > > We are now duplicating information from sspp to dpu caps for convenience > and nothing wrong with it if the helper will get called like every > atomic check . > > But looking at the next patch, it seems we use this information only > once during dpu_plane_init(), so why not add a helper to find this out? Sure, why not. > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ > > 2 files changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > > index 2d6944a9679a..33527ec7c938 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > > @@ -489,6 +489,7 @@ static const struct dpu_caps sc7280_dpu_caps = { > > .ubwc_version = DPU_HW_UBWC_VER_30, > > .has_dim_layer = true, > > .has_idle_pc = true, > > + .has_inline_rot = true, > > .max_linewidth = 2400, > > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > > .format_list = plane_formats_yuv, > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > > index 4847aae78db2..cc64fb2e815f 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > > @@ -400,6 +400,7 @@ struct dpu_rotation_cfg { > > * @has_dim_layer dim layer feature status > > * @has_idle_pc indicate if idle power collapse feature is supported > > * @has_3d_merge indicate if 3D merge is supported > > + * @has_inline_rot indicate if inline rotation is supported > > * @max_linewidth max linewidth for sspp > > * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes > > * @max_hdeci_exp max horizontal decimation supported (max is 2^value) > > @@ -416,6 +417,7 @@ struct dpu_caps { > > bool has_dim_layer; > > bool has_idle_pc; > > bool has_3d_merge; > > + bool has_inline_rot; > > /* SSPP limits */ > > u32 max_linewidth; > > u32 pixel_ram_size;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 2d6944a9679a..33527ec7c938 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -489,6 +489,7 @@ static const struct dpu_caps sc7280_dpu_caps = { .ubwc_version = DPU_HW_UBWC_VER_30, .has_dim_layer = true, .has_idle_pc = true, + .has_inline_rot = true, .max_linewidth = 2400, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, .format_list = plane_formats_yuv, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4847aae78db2..cc64fb2e815f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -400,6 +400,7 @@ struct dpu_rotation_cfg { * @has_dim_layer dim layer feature status * @has_idle_pc indicate if idle power collapse feature is supported * @has_3d_merge indicate if 3D merge is supported + * @has_inline_rot indicate if inline rotation is supported * @max_linewidth max linewidth for sspp * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes * @max_hdeci_exp max horizontal decimation supported (max is 2^value) @@ -416,6 +417,7 @@ struct dpu_caps { bool has_dim_layer; bool has_idle_pc; bool has_3d_merge; + bool has_inline_rot; /* SSPP limits */ u32 max_linewidth; u32 pixel_ram_size;
We need to know if the platform supports inline rotation on any of the SSPP blocks or not. Add this information to struct dpu_caps in a form of the boolean field has_inline_rot. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ 2 files changed, 3 insertions(+)