| Message ID | 20230314132437.121534-2-xingyu.wu@starfivetech.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add watchdog driver for StarFive JH7100/JH7110 RISC-V SoCs | expand |
On Tue, Mar 14, 2023 at 09:24:35PM +0800, Xingyu Wu wrote: > Add bindings to describe the watchdog for the StarFive JH7100/JH7110 SoC. > And Use JH7100 as first StarFive SoC with watchdog. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > .../watchdog/starfive,jh7100-wdt.yaml | 71 +++++++++++++++++++ > 1 file changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml > > diff --git a/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml > new file mode 100644 > index 000000000000..68f3f6fd08a6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive Watchdog for JH7100 and JH7110 SoC > + > +maintainers: > + - Xingyu Wu <xingyu.wu@starfivetech.com> > + - Samin Guo <samin.guo@starfivetech.com> > + > +description: > + The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog > + has only one timeout phase and reboots. And JH7110 watchdog has two > + timeout phases. At the first phase, the signal of watchdog interrupt > + output(WDOGINT) will rise when counter is 0. The counter will reload > + the timeout value. And then, if counter decreases to 0 again and WDOGINT > + isn't cleared, the watchdog will reset the system unless the watchdog > + reset is disabled. > + > +allOf: > + - $ref: watchdog.yaml# > + > +properties: > + compatible: > + enum: > + - starfive,jh7100-wdt > + - starfive,jh7110-wdt > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: APB clock > + - description: Core clock > + > + clock-names: > + items: > + - const: apb > + - const: core > + > + resets: > + items: > + - description: APB reset > + - description: Core reset > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + > +unevaluatedProperties: false > + > +examples: > + - | > + watchdog@12480000 { > + compatible = "starfive,jh7100-wdt"; > + reg = <0x12480000 0x10000>; > + clocks = <&clk 171>, > + <&clk 172>; > + clock-names = "apb", "core"; > + resets = <&rst 99>, > + <&rst 100>; > + };
diff --git a/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml new file mode 100644 index 000000000000..68f3f6fd08a6 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive Watchdog for JH7100 and JH7110 SoC + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + - Samin Guo <samin.guo@starfivetech.com> + +description: + The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog + has only one timeout phase and reboots. And JH7110 watchdog has two + timeout phases. At the first phase, the signal of watchdog interrupt + output(WDOGINT) will rise when counter is 0. The counter will reload + the timeout value. And then, if counter decreases to 0 again and WDOGINT + isn't cleared, the watchdog will reset the system unless the watchdog + reset is disabled. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - starfive,jh7100-wdt + - starfive,jh7110-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: APB clock + - description: Core clock + + clock-names: + items: + - const: apb + - const: core + + resets: + items: + - description: APB reset + - description: Core reset + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + watchdog@12480000 { + compatible = "starfive,jh7100-wdt"; + reg = <0x12480000 0x10000>; + clocks = <&clk 171>, + <&clk 172>; + clock-names = "apb", "core"; + resets = <&rst 99>, + <&rst 100>; + };