diff mbox series

[PULL,07/21] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml

Message ID 20230306153435.490894-8-peter.maydell@linaro.org
State Accepted
Commit fdfb214cf05a186e573fc337972d5b169edc942a
Headers show
Series [PULL,01/21] target/arm: Normalize aarch64 gdbstub get/set function names | expand

Commit Message

Peter Maydell March 6, 2023, 3:34 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>

Define svep based on the size of the predicates,
not the primary vector registers.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 895e19f0845..d0e1305f6fc 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -297,7 +297,7 @@  int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
     /* Create the predicate vector type. */
     g_string_append_printf(s,
                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
-                           reg_width / 8);
+                           pred_width / 8);
 
     /* Define the vector registers. */
     for (i = 0; i < 32; i++) {