| Message ID | 20230223141402.23979-1-swati.agarwal@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | mmc: sdhci-of-arasan: Add support to request the "gate" clock | expand |
On 2/23/23 15:14, Swati Agarwal wrote: > Add support to read the optional "gate" clock property and request the > clock which will be used to ungate the DLL clock. > > For Xilinx platforms which has DLL module, dll clock must be > ungated/enabled when SD controller operates at higher frequencies like 50 > MHz, 100 MHz and 200 MHz. This will be done by explicitly requesting gate > clock from the driver. > > Signed-off-by: Swati Agarwal <swati.agarwal@amd.com> > --- > drivers/mmc/host/sdhci-of-arasan.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c > index 4eebbf801b41..1fd7528c14fc 100644 > --- a/drivers/mmc/host/sdhci-of-arasan.c > +++ b/drivers/mmc/host/sdhci-of-arasan.c > @@ -1870,6 +1870,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) > int ret; > struct device_node *node; > struct clk *clk_xin; > + struct clk *clk_dll; > struct sdhci_host *host; > struct sdhci_pltfm_host *pltfm_host; > struct device *dev = &pdev->dev; > @@ -1943,6 +1944,12 @@ static int sdhci_arasan_probe(struct platform_device *pdev) > goto clk_dis_ahb; > } > > + clk_dll = devm_clk_get_optional_enabled(dev, "gate"); > + if (IS_ERR(clk_dll)) { > + ret = dev_err_probe(dev, PTR_ERR(clk_dll), "failed to get dll clk\n"); > + goto clk_disable_all; > + } > + > if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) > sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; > Based on available information, that it is not clear what gate clock really is and what it is used for, I think the patch is correct. Acked-by: Michal Simek <michal.simek@amd.com> Thanks, Michal
On Thu, 23 Feb 2023 at 15:14, Swati Agarwal <swati.agarwal@amd.com> wrote: > > Add support to read the optional "gate" clock property and request the > clock which will be used to ungate the DLL clock. > > For Xilinx platforms which has DLL module, dll clock must be > ungated/enabled when SD controller operates at higher frequencies like 50 > MHz, 100 MHz and 200 MHz. This will be done by explicitly requesting gate > clock from the driver. I guess we need to update the DT bindings too? Kind regards Uffe > > Signed-off-by: Swati Agarwal <swati.agarwal@amd.com> > --- > drivers/mmc/host/sdhci-of-arasan.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c > index 4eebbf801b41..1fd7528c14fc 100644 > --- a/drivers/mmc/host/sdhci-of-arasan.c > +++ b/drivers/mmc/host/sdhci-of-arasan.c > @@ -1870,6 +1870,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) > int ret; > struct device_node *node; > struct clk *clk_xin; > + struct clk *clk_dll; > struct sdhci_host *host; > struct sdhci_pltfm_host *pltfm_host; > struct device *dev = &pdev->dev; > @@ -1943,6 +1944,12 @@ static int sdhci_arasan_probe(struct platform_device *pdev) > goto clk_dis_ahb; > } > > + clk_dll = devm_clk_get_optional_enabled(dev, "gate"); > + if (IS_ERR(clk_dll)) { > + ret = dev_err_probe(dev, PTR_ERR(clk_dll), "failed to get dll clk\n"); > + goto clk_disable_all; > + } > + > if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) > sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; > > -- > 2.17.1 >
On 2/27/23 15:56, Ulf Hansson wrote: > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > On Thu, 23 Feb 2023 at 15:14, Swati Agarwal <swati.agarwal@amd.com> wrote: >> >> Add support to read the optional "gate" clock property and request the >> clock which will be used to ungate the DLL clock. >> >> For Xilinx platforms which has DLL module, dll clock must be >> ungated/enabled when SD controller operates at higher frequencies like 50 >> MHz, 100 MHz and 200 MHz. This will be done by explicitly requesting gate >> clock from the driver. > > I guess we need to update the DT bindings too? DT binding has it already. It is just not used. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml?h=v6.2#n110 Thanks, Michal
On Mon, 27 Feb 2023 at 16:09, Michal Simek <michal.simek@amd.com> wrote: > > > > On 2/27/23 15:56, Ulf Hansson wrote: > > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > > > > On Thu, 23 Feb 2023 at 15:14, Swati Agarwal <swati.agarwal@amd.com> wrote: > >> > >> Add support to read the optional "gate" clock property and request the > >> clock which will be used to ungate the DLL clock. > >> > >> For Xilinx platforms which has DLL module, dll clock must be > >> ungated/enabled when SD controller operates at higher frequencies like 50 > >> MHz, 100 MHz and 200 MHz. This will be done by explicitly requesting gate > >> clock from the driver. > > > > I guess we need to update the DT bindings too? > > DT binding has it already. It is just not used. > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml?h=v6.2#n110 Aha, thanks for the pointer! Kind regards Uffe
On 23/02/23 16:14, Swati Agarwal wrote: > Add support to read the optional "gate" clock property and request the > clock which will be used to ungate the DLL clock. > > For Xilinx platforms which has DLL module, dll clock must be > ungated/enabled when SD controller operates at higher frequencies like 50 > MHz, 100 MHz and 200 MHz. This will be done by explicitly requesting gate > clock from the driver. > > Signed-off-by: Swati Agarwal <swati.agarwal@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > drivers/mmc/host/sdhci-of-arasan.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c > index 4eebbf801b41..1fd7528c14fc 100644 > --- a/drivers/mmc/host/sdhci-of-arasan.c > +++ b/drivers/mmc/host/sdhci-of-arasan.c > @@ -1870,6 +1870,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) > int ret; > struct device_node *node; > struct clk *clk_xin; > + struct clk *clk_dll; > struct sdhci_host *host; > struct sdhci_pltfm_host *pltfm_host; > struct device *dev = &pdev->dev; > @@ -1943,6 +1944,12 @@ static int sdhci_arasan_probe(struct platform_device *pdev) > goto clk_dis_ahb; > } > > + clk_dll = devm_clk_get_optional_enabled(dev, "gate"); > + if (IS_ERR(clk_dll)) { > + ret = dev_err_probe(dev, PTR_ERR(clk_dll), "failed to get dll clk\n"); > + goto clk_disable_all; > + } > + > if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) > sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; >
On Thu, 23 Feb 2023 at 15:14, Swati Agarwal <swati.agarwal@amd.com> wrote: > > Add support to read the optional "gate" clock property and request the > clock which will be used to ungate the DLL clock. > > For Xilinx platforms which has DLL module, dll clock must be > ungated/enabled when SD controller operates at higher frequencies like 50 > MHz, 100 MHz and 200 MHz. This will be done by explicitly requesting gate > clock from the driver. > > Signed-off-by: Swati Agarwal <swati.agarwal@amd.com> Applied for next, thanks! Kind regards Uffe > --- > drivers/mmc/host/sdhci-of-arasan.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c > index 4eebbf801b41..1fd7528c14fc 100644 > --- a/drivers/mmc/host/sdhci-of-arasan.c > +++ b/drivers/mmc/host/sdhci-of-arasan.c > @@ -1870,6 +1870,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) > int ret; > struct device_node *node; > struct clk *clk_xin; > + struct clk *clk_dll; > struct sdhci_host *host; > struct sdhci_pltfm_host *pltfm_host; > struct device *dev = &pdev->dev; > @@ -1943,6 +1944,12 @@ static int sdhci_arasan_probe(struct platform_device *pdev) > goto clk_dis_ahb; > } > > + clk_dll = devm_clk_get_optional_enabled(dev, "gate"); > + if (IS_ERR(clk_dll)) { > + ret = dev_err_probe(dev, PTR_ERR(clk_dll), "failed to get dll clk\n"); > + goto clk_disable_all; > + } > + > if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) > sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; > > -- > 2.17.1 >
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 4eebbf801b41..1fd7528c14fc 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -1870,6 +1870,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) int ret; struct device_node *node; struct clk *clk_xin; + struct clk *clk_dll; struct sdhci_host *host; struct sdhci_pltfm_host *pltfm_host; struct device *dev = &pdev->dev; @@ -1943,6 +1944,12 @@ static int sdhci_arasan_probe(struct platform_device *pdev) goto clk_dis_ahb; } + clk_dll = devm_clk_get_optional_enabled(dev, "gate"); + if (IS_ERR(clk_dll)) { + ret = dev_err_probe(dev, PTR_ERR(clk_dll), "failed to get dll clk\n"); + goto clk_disable_all; + } + if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
Add support to read the optional "gate" clock property and request the clock which will be used to ungate the DLL clock. For Xilinx platforms which has DLL module, dll clock must be ungated/enabled when SD controller operates at higher frequencies like 50 MHz, 100 MHz and 200 MHz. This will be done by explicitly requesting gate clock from the driver. Signed-off-by: Swati Agarwal <swati.agarwal@amd.com> --- drivers/mmc/host/sdhci-of-arasan.c | 7 +++++++ 1 file changed, 7 insertions(+)