@@ -379,17 +379,25 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
}
static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
- target_ulong *cs_base, uint32_t *flags)
+ target_ulong *cs_base, uint32_t *pflags)
{
- *pc = env->psw.addr;
- *cs_base = env->ex_value;
- *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
+ int flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
if (env->cregs[0] & CR0_AFP) {
- *flags |= FLAG_MASK_AFP;
+ flags |= FLAG_MASK_AFP;
}
if (env->cregs[0] & CR0_VECTOR) {
- *flags |= FLAG_MASK_VECTOR;
+ flags |= FLAG_MASK_VECTOR;
}
+ *pflags = flags;
+ *cs_base = env->ex_value;
+ *pc = env->psw.addr;
+#ifdef CONFIG_DEBUG_TCG
+ if (!(flags & FLAG_MASK_32)) {
+ assert(*pc <= 0xffffff);
+ } else if (!(flags & FLAG_MASK_64)) {
+ assert(*pc <= 0x7fffffff);
+ }
+#endif
}
/* PER bits from control register 9 */
@@ -6563,11 +6563,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- /* 31-bit mode */
- if (!(dc->base.tb->flags & FLAG_MASK_64)) {
- dc->base.pc_first &= 0x7fffffff;
- dc->base.pc_next = dc->base.pc_first;
- }
+ /* Note cpu_get_tb_cpu_state asserts PC is masked for the mode. */
dc->cc_op = CC_OP_DYNAMIC;
dc->ex_value = dc->base.tb->cs_base;