@@ -87,6 +87,12 @@ extern const struct tb_nhi_ops icl_nhi_ops;
#define PCI_DEVICE_ID_INTEL_RPL_NHI0 0xa73e
#define PCI_DEVICE_ID_INTEL_RPL_NHI1 0xa76d
+/* PCI IDs for AMD USB4 controllers */
+#define PCI_DEVICE_ID_AMD_YELLOW_CARP_NHI0 0x162e
+#define PCI_DEVICE_ID_AMD_YELLOW_CARP_NHI1 0x162f
+#define PCI_DEVICE_ID_AMD_PINK_SARDINE_NHI0 0x1668
+#define PCI_DEVICE_ID_AMD_PINK_SARDINE_NHI1 0x1669
+
#define PCI_CLASS_SERIAL_USB_USB4 0x0c0340
#endif
@@ -3574,6 +3574,12 @@ int tb_switch_enable_clx(struct tb_switch *sw, enum tb_clx clx)
if (root_sw->generation < 4 || tb_switch_is_tiger_lake(root_sw))
return 0;
+ /*
+ * Disabling CLx by default on AMD USB4 platforms for Yellow Carp and Pink Sardine.
+ */
+ if (tb_switch_is_yellow_carp(sw->tb->nhi) || tb_switch_is_pink_sardine(sw->tb->nhi))
+ return 0;
+
switch (clx) {
case TB_CL1:
/* CL0s and CL1 are enabled and supported together */
@@ -905,6 +905,30 @@ static inline bool tb_switch_is_tiger_lake(const struct tb_switch *sw)
return false;
}
+static inline bool tb_switch_is_yellow_carp(const struct tb_nhi *nhi)
+{
+ if (nhi->pdev->vendor == PCI_VENDOR_ID_AMD) {
+ switch (nhi->pdev->device) {
+ case PCI_DEVICE_ID_AMD_YELLOW_CARP_NHI0:
+ case PCI_DEVICE_ID_AMD_YELLOW_CARP_NHI1:
+ return true;
+ }
+ }
+ return false;
+}
+
+static inline bool tb_switch_is_pink_sardine(const struct tb_nhi *nhi)
+{
+ if (nhi->pdev->vendor == PCI_VENDOR_ID_AMD) {
+ switch (nhi->pdev->device) {
+ case PCI_DEVICE_ID_AMD_PINK_SARDINE_NHI0:
+ case PCI_DEVICE_ID_AMD_PINK_SARDINE_NHI1:
+ return true;
+ }
+ }
+ return false;
+}
+
/**
* tb_switch_is_usb4() - Is the switch USB4 compliant
* @sw: Switch to check